Module Definition
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Module Instance : tb.dut.u_tlul_lc_gate_sba

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.13 86.27 72.22 57.14 75.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
74.11 89.76 64.29 57.14 71.88 87.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.35 87.88 61.70 87.54 57.14 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h 100.00 100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d 100.00 100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h 100.00 100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d 100.00 100.00
u_err_en_sync 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_tlul_err_resp 71.59 86.36 50.00 50.00 100.00



Module Instance : tb.dut.u_tlul_lc_gate_rom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
81.44 96.08 77.78 100.00 83.33 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.44 93.70 67.86 100.00 78.12 87.50


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
76.35 87.88 61.70 87.54 57.14 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_lc_gating_muxes[0].u_prim_blanker_d2h 100.00 100.00
gen_lc_gating_muxes[0].u_prim_blanker_h2d 100.00 100.00
gen_lc_gating_muxes[1].u_prim_blanker_d2h 100.00 100.00
gen_lc_gating_muxes[1].u_prim_blanker_h2d 100.00 100.00
u_err_en_sync 100.00 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_tlul_err_resp 71.59 86.36 50.00 50.00 100.00

Line Coverage for Module : tlul_lc_gate
Line No.TotalCoveredPercent
TOTAL514996.08
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
ALWAYS14433100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
ALWAYS15366100.00
ALWAYS164282692.86
ALWAYS2301010100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
85 1 1
144 3 3
149 1 1
150 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
169 1 1
171 1 1
173 1 1
174 1 1
MISSING_ELSE
176 1 1
177 1 1
MISSING_ELSE
182 1 1
183 1 1
184 1 1
186 0 1
191 1 1
192 1 1
193 1 1
194 0 1
195 1 1
196 1 1
MISSING_ELSE
201 1 1
202 1 1
203 1 1
MISSING_ELSE
208 1 1
209 1 1
210 1 1
211 1 1
==> MISSING_ELSE
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
MISSING_ELSE
239 1 1
240 1 1
241 1 1
242 1 1
MISSING_ELSE


Cond Coverage for Module : tlul_lc_gate
TotalCoveredPercent
Conditions181477.78
Logical181477.78
Non-Logical00
Event00

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T28
11CoveredT2,T4,T28

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT2,T6,T9
10CoveredT1,T2,T3
11CoveredT2,T4,T28

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T28

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T28

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T28

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT32,T9,T22

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

FSM Coverage for Module : tlul_lc_gate
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StActive 196 Covered T1,T2,T3
StError 184 Covered T1,T2,T3
StErrorOutstanding 203 Covered T1,T2,T3
StFlush 184 Covered T9,T22,T17
StOutstanding 174 Covered T32,T9,T22


transitionsLine No.CoveredTests
StActive->StOutstanding 174 Covered T32,T9,T22
StError->StErrorOutstanding 203 Covered T1,T2,T3
StErrorOutstanding->StActive 211 Covered T1,T2,T3
StFlush->StActive 196 Covered T9,T22,T17
StFlush->StError 194 Covered T60
StOutstanding->StError 184 Covered T32,T42
StOutstanding->StFlush 184 Covered T9,T22,T17



Branch Coverage for Module : tlul_lc_gate
Line No.TotalCoveredPercent
Branches 24 20 83.33
IF 144 2 2 100.00
IF 153 4 4 100.00
CASE 171 14 10 71.43
IF 234 2 2 100.00
IF 239 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 153 if ((!rst_ni)) -2-: 155 if ((a_ack && (!d_ack))) -3-: 157 if ((d_ack && (!a_ack)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T4,T28
0 0 1 Covered T2,T4,T28
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 171 case (state_q) -2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i)) -3-: 176 if ((outstanding_txn != '0)) -4-: 183 if ((outstanding_txn == '0)) -5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i)) -6-: 195 if ((!flush_req_i)) -7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i)) -8-: 210 if ((outstanding_txn == '0))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StActive 1 - - - - - - Covered T32,T9,T22
StActive 0 - - - - - - Covered T1,T2,T3
StActive - 1 - - - - - Covered T2,T4,T28
StActive - 0 - - - - - Covered T1,T2,T3
StOutstanding - - 1 - - - - Covered T32,T9,T22
StOutstanding - - 0 - - - - Not Covered
StFlush - - - 1 - - - Not Covered
StFlush - - - 0 1 - - Covered T9,T22,T17
StFlush - - - 0 0 - - Covered T9,T22,T17
StError - - - - - 1 - Covered T1,T2,T3
StError - - - - - 0 - Covered T1,T2,T3
StErrorOutstanding - - - - - - 1 Covered T1,T2,T3
StErrorOutstanding - - - - - - 0 Not Covered
default - - - - - - - Not Covered


LineNo. Expression -1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 239 if (block_cmd)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_lc_gate
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutStandingOvfl_A 4456170 0 0 0
u_state_regs_A 4456170 4428228 0 0


OutStandingOvfl_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4456170 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 4456170 4428228 0 0
T1 15452 15344 0 0
T2 26944 26752 0 0
T3 2460 2330 0 0
T4 410072 409948 0 0
T5 2282 2166 0 0
T28 847080 844080 0 0
T40 2180 2056 0 0
T41 4864 4734 0 0
T43 2078 1954 0 0
T49 4344 4232 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
Line No.TotalCoveredPercent
TOTAL514486.27
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
ALWAYS14433100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
ALWAYS15366100.00
ALWAYS164282175.00
ALWAYS2301010100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
85 1 1
144 3 3
149 1 1
150 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
169 1 1
171 1 1
173 1 1
174 1 1
MISSING_ELSE
176 1 1
177 1 1
MISSING_ELSE
182 1 1
183 1 1
184 1 1
186 0 1
191 0 1
192 0 1
193 0 1
194 0 1
195 0 1
196 0 1
==> MISSING_ELSE
201 1 1
202 1 1
203 1 1
MISSING_ELSE
208 1 1
209 1 1
210 1 1
211 1 1
==> MISSING_ELSE
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
MISSING_ELSE
239 1 1
240 1 1
241 1 1
242 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
TotalCoveredPercent
Conditions181372.22
Logical181372.22
Non-Logical00
Event00

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T29,T61
11CoveredT28,T29,T30

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT28,T29,T30

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT28,T29,T30

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT28,T29,T30

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T29,T30

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT32,T42

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
Summary for FSM :: state_q
TotalCoveredPercent
States 5 4 80.00 (Not included in score)
Transitions 7 4 57.14
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StActive 196 Covered T1,T2,T3
StError 184 Covered T1,T2,T3
StErrorOutstanding 203 Covered T1,T2,T3
StFlush 184 Not Covered
StOutstanding 174 Covered T32,T42


transitionsLine No.CoveredTests
StActive->StOutstanding 174 Covered T32,T42
StError->StErrorOutstanding 203 Covered T1,T2,T3
StErrorOutstanding->StActive 211 Covered T1,T2,T3
StFlush->StActive 196 Not Covered
StFlush->StError 194 Not Covered
StOutstanding->StError 184 Covered T32,T42
StOutstanding->StFlush 184 Not Covered



Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
Line No.TotalCoveredPercent
Branches 24 18 75.00
IF 144 2 2 100.00
IF 153 4 4 100.00
CASE 171 14 8 57.14
IF 234 2 2 100.00
IF 239 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 153 if ((!rst_ni)) -2-: 155 if ((a_ack && (!d_ack))) -3-: 157 if ((d_ack && (!a_ack)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T28,T29,T30
0 0 1 Covered T28,T29,T30
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 171 case (state_q) -2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i)) -3-: 176 if ((outstanding_txn != '0)) -4-: 183 if ((outstanding_txn == '0)) -5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i)) -6-: 195 if ((!flush_req_i)) -7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i)) -8-: 210 if ((outstanding_txn == '0))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StActive 1 - - - - - - Covered T32,T42
StActive 0 - - - - - - Covered T1,T2,T3
StActive - 1 - - - - - Covered T28,T29,T30
StActive - 0 - - - - - Covered T1,T2,T3
StOutstanding - - 1 - - - - Covered T32,T42
StOutstanding - - 0 - - - - Not Covered
StFlush - - - 1 - - - Not Covered
StFlush - - - 0 1 - - Not Covered
StFlush - - - 0 0 - - Not Covered
StError - - - - - 1 - Covered T1,T2,T3
StError - - - - - 0 - Covered T1,T2,T3
StErrorOutstanding - - - - - - 1 Covered T1,T2,T3
StErrorOutstanding - - - - - - 0 Not Covered
default - - - - - - - Not Covered


LineNo. Expression -1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 239 if (block_cmd)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutStandingOvfl_A 2228085 0 0 0
u_state_regs_A 2228085 2214114 0 0


OutStandingOvfl_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2228085 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2228085 2214114 0 0
T1 7726 7672 0 0
T2 13472 13376 0 0
T3 1230 1165 0 0
T4 205036 204974 0 0
T5 1141 1083 0 0
T28 423540 422040 0 0
T40 1090 1028 0 0
T41 2432 2367 0 0
T43 1039 977 0 0
T49 2172 2116 0 0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
Line No.TotalCoveredPercent
TOTAL514996.08
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
ALWAYS14433100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN15011100.00
ALWAYS15366100.00
ALWAYS164282692.86
ALWAYS2301010100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
84 1 1
85 1 1
144 3 3
149 1 1
150 1 1
153 1 1
154 1 1
155 1 1
156 1 1
157 1 1
158 1 1
MISSING_ELSE
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
169 1 1
171 1 1
173 1 1
174 1 1
MISSING_ELSE
176 1 1
177 1 1
MISSING_ELSE
182 1 1
183 1 1
184 1 1
186 0 1
191 1 1
192 1 1
193 1 1
194 0 1
195 1 1
196 1 1
MISSING_ELSE
201 1 1
202 1 1
203 1 1
MISSING_ELSE
208 1 1
209 1 1
210 1 1
211 1 1
==> MISSING_ELSE
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
MISSING_ELSE
239 1 1
240 1 1
241 1 1
242 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
TotalCoveredPercent
Conditions181477.78
Logical181477.78
Non-Logical00
Event00

 LINE       149
 EXPRESSION (tl_h2d_i.a_valid & tl_d2h_o.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T6
11CoveredT2,T4,T6

 LINE       150
 EXPRESSION (tl_h2d_i.d_ready & tl_d2h_o.d_valid)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT2,T6,T9
10CoveredT1,T2,T3
11CoveredT2,T4,T6

 LINE       155
 EXPRESSION (a_ack && ((!d_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T6

 LINE       157
 EXPRESSION (d_ack && ((!a_ack)))
             --1--    -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T4,T6

 LINE       176
 EXPRESSION (outstanding_txn != '0)
            -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T4,T6

 LINE       183
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT32,T9,T22

 LINE       210
 EXPRESSION (outstanding_txn == '0)
            -----------1-----------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

FSM Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
Summary for FSM :: state_q
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 7 7 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StActive 196 Covered T1,T2,T3
StError 184 Covered T1,T2,T3
StErrorOutstanding 203 Covered T1,T2,T3
StFlush 184 Covered T9,T22,T17
StOutstanding 174 Covered T32,T9,T22


transitionsLine No.CoveredTests
StActive->StOutstanding 174 Covered T32,T9,T22
StError->StErrorOutstanding 203 Covered T1,T2,T3
StErrorOutstanding->StActive 211 Covered T1,T2,T3
StFlush->StActive 196 Covered T9,T22,T17
StFlush->StError 194 Covered T60
StOutstanding->StError 184 Covered T32,T42
StOutstanding->StFlush 184 Covered T9,T22,T17



Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
Line No.TotalCoveredPercent
Branches 24 20 83.33
IF 144 2 2 100.00
IF 153 4 4 100.00
CASE 171 14 10 71.43
IF 234 2 2 100.00
IF 239 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv' or '../src/lowrisc_tlul_lc_gate_0.1/rtl/tlul_lc_gate.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 153 if ((!rst_ni)) -2-: 155 if ((a_ack && (!d_ack))) -3-: 157 if ((d_ack && (!a_ack)))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T4,T6
0 0 1 Covered T2,T4,T6
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 171 case (state_q) -2-: 173 if ((lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i) || flush_req_i)) -3-: 176 if ((outstanding_txn != '0)) -4-: 183 if ((outstanding_txn == '0)) -5-: 193 if (lc_ctrl_pkg::lc_tx_test_false_loose(lc_en_i)) -6-: 195 if ((!flush_req_i)) -7-: 202 if (lc_ctrl_pkg::lc_tx_test_true_strict(lc_en_i)) -8-: 210 if ((outstanding_txn == '0))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StActive 1 - - - - - - Covered T32,T9,T22
StActive 0 - - - - - - Covered T1,T2,T3
StActive - 1 - - - - - Covered T2,T4,T6
StActive - 0 - - - - - Covered T1,T2,T3
StOutstanding - - 1 - - - - Covered T32,T9,T22
StOutstanding - - 0 - - - - Not Covered
StFlush - - - 1 - - - Not Covered
StFlush - - - 0 1 - - Covered T9,T22,T17
StFlush - - - 0 0 - - Covered T9,T22,T17
StError - - - - - 1 - Covered T1,T2,T3
StError - - - - - 0 - Covered T1,T2,T3
StErrorOutstanding - - - - - - 1 Covered T1,T2,T3
StErrorOutstanding - - - - - - 0 Not Covered
default - - - - - - - Not Covered


LineNo. Expression -1-: 234 if (lc_ctrl_pkg::lc_tx_test_true_loose(err_en))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 239 if (block_cmd)

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutStandingOvfl_A 2228085 0 0 0
u_state_regs_A 2228085 2214114 0 0


OutStandingOvfl_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2228085 0 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2228085 2214114 0 0
T1 7726 7672 0 0
T2 13472 13376 0 0
T3 1230 1165 0 0
T4 205036 204974 0 0
T5 1141 1083 0 0
T28 423540 422040 0 0
T40 1090 1028 0 0
T41 2432 2367 0 0
T43 1039 977 0 0
T49 2172 2116 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%