Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.96	90.91	61.70	87.54		57.14	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	25494009	12465	0	0
late_debug_enable_rd_A	25494009	1560	0	0
late_debug_enable_regwen_rd_A	25494009	1846	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25494009	12465	0	0
T39	294320	24	0	0
T40	107338	6	0	0
T41	3603	114	0	0
T72	292469	33	0	0
T78	63771	2	0	0
T89	6612	713	0	0
T90	8162	606	0	0
T91	189224	369	0	0
T92	46807	35	0	0
T93	15477	55	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25494009	1560	0	0
T39	294320	30	0	0
T43	19485	31	0	0
T72	292469	14	0	0
T78	63771	22	0	0
T93	15477	35	0	0
T95	376624	31	0	0
T99	5421	9	0	0
T101	38545	15	0	0
T103	9677	5	0	0
T104	82902	55	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25494009	1846	0	0
T39	294320	30	0	0
T43	19485	21	0	0
T72	292469	35	0	0
T78	63771	46	0	0
T93	15477	31	0	0
T99	5421	1	0	0
T101	38545	14	0	0
T102	5514	5	0	0
T103	9677	6	0	0
T104	82902	71	0	0