Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.96 90.91 61.70 87.54 57.14 87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 76.96 90.91 61.70 87.54 57.14 87.50



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
76.96 90.91 61.70 87.54 57.14 87.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
82.14 90.33 76.92 86.93 64.10 76.17 98.42


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
dap 86.33 98.68 93.42 70.00 94.57 75.00
gen_alert_tx[0].u_prim_alert_sender 83.33 83.33
i_tlul_adapter_reg 93.27 99.00 80.90 93.33 93.10 100.00
rv_dm_regs_csr_assert 100.00 100.00
tl_adapter_host_sba 85.52 97.67 77.78 72.14 80.00 100.00
tlul_assert_device_mem 95.24 100.00 85.71 100.00
tlul_assert_device_regs 95.24 100.00 85.71 100.00
tlul_assert_host_sba 64.34 53.33 42.86 96.83
u_dm_top 61.96 74.62 52.33 28.57 54.26 100.00
u_lc_en_sync_copies 100.00 100.00 100.00
u_pm_en_sync 100.00 100.00 100.00 100.00
u_prim_clock_mux2 100.00 100.00 100.00 100.00
u_prim_flop_2sync_lc_rst_assert 100.00 100.00 100.00
u_prim_flop_2sync_lc_rst_sync 100.00 100.00 100.00
u_prim_lc_sync_lc_dft_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_lc_hw_debug_en 100.00 100.00 100.00 100.00
u_prim_mubi32_sync_late_debug_enable 100.00 100.00 100.00
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00 100.00
u_prim_rst_n_mux2 100.00 100.00 100.00 100.00
u_reg_regs 98.19 98.69 98.71 93.55 100.00 100.00
u_tlul_lc_gate_rom 85.44 93.70 67.86 100.00 78.12 87.50
u_tlul_lc_gate_sba 67.48 87.40 42.86 57.14 62.50 87.50


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm
Line No.TotalCoveredPercent
TOTAL333090.91
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN15411100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN28911100.00
ALWAYS32011872.73
CONT_ASSIGN34511100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43811100.00
CONT_ASSIGN44011100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
122 1 1
123 1 1
128 1 1
131 1 1
154 1 1
236 1 1
237 1 1
239 4 4
278 1 1
288 1 1
289 1 1
320 1 1
321 1 1
322 1 1
325 1 1
326 1 1
327 1 1
328 0 1
MISSING_ELSE
331 1 1
332 0 1
333 1 1
334 0 1
MISSING_ELSE
345 1 1
432 1 1
438 1 1
440 1 1
446 1 1
447 1 1
523 1 1
551 1 1


Cond Coverage for Module : rv_dm
TotalCoveredPercent
Conditions472961.70
Logical472961.70
Non-Logical00
Event00

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100Not Covered
1000CoveredT30,T31,T32

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT2,T33,T34
10CoveredT2,T17,T33
11CoveredT2,T33,T35

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T26,T16

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T26,T16
11CoveredT5,T26,T16

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------
-1--2-StatusTests
01CoveredT5,T26,T16
10Not Covered
11Not Covered

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T26,T16
11Not Covered

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----
-1--2--3--4--5-StatusTests
01111Not Covered
10111CoveredT5,T26,T16
11011Not Covered
11101Not Covered
11110Not Covered
11111Not Covered

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T3,T7

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T20,T14
11CoveredT1,T2,T3

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T5,T27
10CoveredT1,T3,T7

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T20,T14
11CoveredT1,T2,T3

Toggle Coverage for Module : rv_dm
TotalCoveredPercent
Totals 98 78 79.59
Total Bits 1188 1040 87.54
Total Bits 0->1 594 520 87.54
Total Bits 1->0 594 520 87.54

Ports 98 78 79.59
Port Bits 1188 1040 87.54
Port Bits 0->1 594 520 87.54
Port Bits 1->0 594 520 87.54

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_lc_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T5,T30,T6 Yes T1,T2,T3 INPUT
rst_lc_ni Yes Yes T5,T30,T6 Yes T1,T2,T3 INPUT
next_dm_addr_i[31:0] No No No INPUT
lc_hw_debug_en_i[3:0] Yes Yes T6,T36,T20 Yes T6,T20,T36 INPUT
lc_dft_en_i[3:0] Yes Yes T6,T36,T20 Yes T6,T20,T36 INPUT
pinmux_hw_debug_en_i[3:0] Yes Yes T6,T36,T20 Yes T6,T20,T36 INPUT
otp_dis_rv_dm_late_debug_i[7:0] Unreachable Unreachable Unreachable INPUT
scanmode_i[0] No No Yes T20,T14 INPUT
scanmode_i[2:1] No Yes T20,T14 No INPUT
scanmode_i[3] No No Yes T20,T14 INPUT
scan_rst_ni Yes Yes T5,T30,T6 Yes T1,T2,T3 INPUT
ndmreset_req_o Yes Yes T5,T26,T16 Yes T5,T26,T16 OUTPUT
dmactive_o Yes Yes T5,T30,T6 Yes T1,T2,T3 OUTPUT
debug_req_o Yes Yes T3,T5,T9 Yes T1,T3,T7 OUTPUT
unavailable_i Yes Yes T3,T4,T17 Yes T17,T37,T5 INPUT
regs_tl_d_i.d_ready Yes Yes T1,T17,T7 Yes T1,T2,T3 INPUT
regs_tl_d_i.a_user.data_intg[6:0] Yes Yes T2,T17,T33 Yes T2,T33,T35 INPUT
regs_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T2,T33,T35 Yes T2,T17,T33 INPUT
regs_tl_d_i.a_user.instr_type[3:0] Yes Yes T2,T35,T8 Yes T2,T35,T38 INPUT
regs_tl_d_i.a_user.rsvd[4:0] Yes Yes T2,T35,T38 Yes T2,T17,T35 INPUT
regs_tl_d_i.a_data[31:0] Yes Yes T2,T33,T35 Yes T2,T33,T35 INPUT
regs_tl_d_i.a_mask[3:0] Yes Yes T2,T17,T35 Yes T2,T35,T38 INPUT
regs_tl_d_i.a_address[31:0] Yes Yes T2,T35,T8 Yes T2,T35,T38 INPUT
regs_tl_d_i.a_source[7:0] Yes Yes T2,T17,T33 Yes T2,T33,T35 INPUT
regs_tl_d_i.a_size[1:0] Yes Yes T2,T33,T35 Yes T2,T33,T34 INPUT
regs_tl_d_i.a_param[2:0] Yes Yes T2,T17,T35 Yes T2,T35,T38 INPUT
regs_tl_d_i.a_opcode[2:0] Yes Yes T2,T33,T34 Yes T2,T33,T35 INPUT
regs_tl_d_i.a_valid Yes Yes T2,T33,T34 Yes T2,T33,T34 INPUT
regs_tl_d_o.a_ready Yes Yes T2,T33,T34 Yes T2,T33,T34 OUTPUT
regs_tl_d_o.d_error Yes Yes T39,T40,T41 Yes T39,T40,T41 OUTPUT
regs_tl_d_o.d_user.data_intg[6:0] Yes Yes T42,T40,T43 Yes T42,T40,T43 OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T2,*T33,*T35 Yes T2,T33,T34 OUTPUT
regs_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_d_o.d_data[31:0] Yes Yes T44,T39,T42 Yes T2,T33,T34 OUTPUT
regs_tl_d_o.d_sink No No No OUTPUT
regs_tl_d_o.d_source[7:0] Yes Yes T33,T45,T46 Yes T33,T35,T45 OUTPUT
regs_tl_d_o.d_size[1:0] Yes Yes T2,T33,T35 Yes T2,T33,T34 OUTPUT
regs_tl_d_o.d_param[2:0] No No No OUTPUT
regs_tl_d_o.d_opcode[0] Yes Yes *T44,*T39,*T42 Yes T44,T39,T42 OUTPUT
regs_tl_d_o.d_opcode[2:1] No No No OUTPUT
regs_tl_d_o.d_valid Yes Yes T2,T33,T34 Yes T2,T33,T34 OUTPUT
mem_tl_d_i.d_ready Yes Yes T1,T17,T7 Yes T1,T2,T3 INPUT
mem_tl_d_i.a_user.data_intg[6:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
mem_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
mem_tl_d_i.a_user.instr_type[3:0] Yes Yes T1,T7,T8 Yes T1,T7,T47 INPUT
mem_tl_d_i.a_user.rsvd[4:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
mem_tl_d_i.a_data[31:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
mem_tl_d_i.a_mask[3:0] Yes Yes T1,T7,T8 Yes T1,T7,T8 INPUT
mem_tl_d_i.a_address[31:0] Yes Yes T1,T7,T8 Yes T1,T7,T47 INPUT
mem_tl_d_i.a_source[7:0] Yes Yes T1,T7,T8 Yes T1,T7,T47 INPUT
mem_tl_d_i.a_size[1:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
mem_tl_d_i.a_param[2:0] Yes Yes T1,T7,T8 Yes T1,T7,T47 INPUT
mem_tl_d_i.a_opcode[2:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
mem_tl_d_i.a_valid Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
mem_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_error Yes Yes T1,T2,T3 Yes T5,T30,T6 OUTPUT
mem_tl_d_o.d_user.data_intg[6:0] Yes Yes T1,T5,T27 Yes T1,T5,T27 OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0] Yes Yes T1,*T3,*T7 Yes T1,T3,T7 OUTPUT
mem_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
mem_tl_d_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T3,T7 OUTPUT
mem_tl_d_o.d_sink No No No OUTPUT
mem_tl_d_o.d_source[7:0] Yes Yes T7,T5,T15 Yes T1,T7,T8 OUTPUT
mem_tl_d_o.d_size[1:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
mem_tl_d_o.d_param[2:0] No No No OUTPUT
mem_tl_d_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T5,T30 OUTPUT
mem_tl_d_o.d_opcode[2:1] No No No OUTPUT
mem_tl_d_o.d_valid Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
sba_tl_h_o.d_ready Yes Yes T5,T30,T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.data_intg[6:0] Yes Yes T48,T49,T50 Yes T48,T49,T50 OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T5,T30,T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[0] Yes Yes *T5,*T30,*T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[2:1] No No No OUTPUT
sba_tl_h_o.a_user.instr_type[3] Yes Yes T5,T30,T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.rsvd[4:0] No No No OUTPUT
sba_tl_h_o.a_data[31:0] Yes Yes T49,T48,T50 Yes T49,T48,T50 OUTPUT
sba_tl_h_o.a_mask[3:0] Yes Yes T5,T30,T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_address[1:0] No No No OUTPUT
sba_tl_h_o.a_address[31:2] Yes Yes T51,T52,T53 Yes T54,T51,T52 OUTPUT
sba_tl_h_o.a_source[7:0] No No No OUTPUT
sba_tl_h_o.a_size[0] No No No OUTPUT
sba_tl_h_o.a_size[1] Yes Yes T5,T30,T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_param[2:0] No No No OUTPUT
sba_tl_h_o.a_opcode[0] Yes Yes *T48,*T55 Yes T48,T55 OUTPUT
sba_tl_h_o.a_opcode[1] No No No OUTPUT
sba_tl_h_o.a_opcode[2] Yes Yes T5,T30,T6 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_valid Yes Yes T48,T50,T56 Yes T48,T50,T56 OUTPUT
sba_tl_h_i.a_ready Yes Yes T1,T17,T7 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_error Yes Yes T57,T9,T58 Yes T9,T59,T60 INPUT
sba_tl_h_i.d_user.data_intg[6:0] Yes Yes T7,T8,T9 Yes T15,T9,T61 INPUT
sba_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T9,T25,T58 Yes T7,T15,T9 INPUT
sba_tl_h_i.d_data[31:0] Yes Yes T8,T57,T9 Yes T9,T62,T14 INPUT
sba_tl_h_i.d_sink Yes Yes T8,T9,T59 Yes T15,T9,T25 INPUT
sba_tl_h_i.d_source[7:0] Yes Yes T58,T63,T62 Yes T46,T62,T14 INPUT
sba_tl_h_i.d_size[1:0] Yes Yes T46,T58,T62 Yes T15,T9,T64 INPUT
sba_tl_h_i.d_param[2:0] Yes Yes T9,T61,T62 Yes T9,T59,T65 INPUT
sba_tl_h_i.d_opcode[0] Yes Yes *T7,*T46,*T57 Yes T8,T15,T9 INPUT
sba_tl_h_i.d_opcode[2:1] No No No INPUT
sba_tl_h_i.d_valid Yes Yes T48,T50,T56 Yes T48,T50,T56 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T2,T33,T35 Yes T2,T33,T35 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T2,T33,T35 Yes T2,T33,T35 OUTPUT
jtag_i.tdi Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.trst_n Yes Yes T5,T30,T6 Yes T1,T2,T3 INPUT
jtag_i.tms Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.tck Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_o.tdo_oe Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
jtag_o.tdo Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rv_dm
Line No.TotalCoveredPercent
Branches 7 4 57.14
IF 320 7 4 57.14

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 320 if ((!rst_ni)) -2-: 325 if ((ndmreset_req && (!ndmreset_pending_q))) -3-: 327 if ((ndmreset_ack && ndmreset_pending_q)) -4-: 331 if ((ndmreset_pending_q && lc_rst_asserted)) -5-: 333 if ((ndmreset_ack && lc_rst_pending_q))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T5,T26,T16
0 0 1 - - Not Covered
0 0 0 - - Covered T1,T2,T3
0 - - 1 - Not Covered
0 - - 0 1 Not Covered
0 - - 0 0 Covered T1,T2,T3


Assert Coverage for Module : rv_dm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 14 87.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 14 87.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DebugReqOKnown_A 1948189 1933986 0 0
DmactiveOKnown_A 1948189 1933986 0 0
FpvSecCmRegWeOnehotCheck_A 1948189 80 0 0
FpvSecCmRomTlLcGateFsm_A 1948189 0 0 0
FpvSecCmSbaTlLcGateFsm_A 1948189 0 0 0
JtagRspOTdoKnown_A 513883 513868 0 0
JtagRspOTdoOeKnown_A 513883 513868 0 0
NdmresetOKnown_A 1948189 1933986 0 0
RvDmLcEnDebugVal_A 1948189 1933986 0 0
TlMemAReadyKnown_A 1948189 1933986 0 0
TlMemDValidKnown_A 1948189 1933986 0 0
TlRegsAReadyKnown_A 1948189 1933986 0 0
TlRegsDValidKnown_A 1948189 1933986 0 0
TlSbaAValidKnown_A 1948189 1933986 0 0
TlSbaDReadyKnown_A 1948189 1933986 0 0
paramCheckNrHarts 97 97 0 0


DebugReqOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1933986 0 0
T1 1960 1892 0 0
T2 1243 1191 0 0
T3 49501 49440 0 0
T4 1452 1389 0 0
T7 79422 79368 0 0
T17 16304 16253 0 0
T33 1831 1751 0 0
T34 1365 1301 0 0
T35 2481 2429 0 0
T45 1673 1593 0 0

DmactiveOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1933986 0 0
T1 1960 1892 0 0
T2 1243 1191 0 0
T3 49501 49440 0 0
T4 1452 1389 0 0
T7 79422 79368 0 0
T17 16304 16253 0 0
T33 1831 1751 0 0
T34 1365 1301 0 0
T35 2481 2429 0 0
T45 1673 1593 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 80 0 0
T6 144263 0 0 0
T15 2976 0 0 0
T19 131740 0 0 0
T30 15859 20 0 0
T31 0 20 0 0
T32 0 20 0 0
T38 1965 0 0 0
T57 3983 0 0 0
T62 0 10 0 0
T66 0 10 0 0
T67 1349 0 0 0
T68 3037 0 0 0
T69 1702 0 0 0
T70 1471 0 0 0

FpvSecCmRomTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 0 0 0

FpvSecCmSbaTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 0 0 0

JtagRspOTdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 513883 513868 0 0
T1 812 812 0 0
T2 154 154 0 0
T3 7021 7021 0 0
T4 408 408 0 0
T7 19903 19903 0 0
T17 3747 3747 0 0
T33 161 161 0 0
T34 180 180 0 0
T35 178 178 0 0
T45 177 177 0 0

JtagRspOTdoOeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 513883 513868 0 0
T1 812 812 0 0
T2 154 154 0 0
T3 7021 7021 0 0
T4 408 408 0 0
T7 19903 19903 0 0
T17 3747 3747 0 0
T33 161 161 0 0
T34 180 180 0 0
T35 178 178 0 0
T45 177 177 0 0

NdmresetOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1933986 0 0
T1 1960 1892 0 0
T2 1243 1191 0 0
T3 49501 49440 0 0
T4 1452 1389 0 0
T7 79422 79368 0 0
T17 16304 16253 0 0
T33 1831 1751 0 0
T34 1365 1301 0 0
T35 2481 2429 0 0
T45 1673 1593 0 0

RvDmLcEnDebugVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1933986 0 0
T1 1960 1892 0 0
T2 1243 1191 0 0
T3 49501 49440 0 0
T4 1452 1389 0 0
T7 79422 79368 0 0
T17 16304 16253 0 0
T33 1831 1751 0 0
T34 1365 1301 0 0
T35 2481 2429 0 0
T45 1673 1593 0 0

TlMemAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1933986 0 0
T1 1960 1892 0 0
T2 1243 1191 0 0
T3 49501 49440 0 0
T4 1452 1389 0 0
T7 79422 79368 0 0
T17 16304 16253 0 0
T33 1831 1751 0 0
T34 1365 1301 0 0
T35 2481 2429 0 0
T45 1673 1593 0 0

TlMemDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1933986 0 0
T1 1960 1892 0 0
T2 1243 1191 0 0
T3 49501 49440 0 0
T4 1452 1389 0 0
T7 79422 79368 0 0
T17 16304 16253 0 0
T33 1831 1751 0 0
T34 1365 1301 0 0
T35 2481 2429 0 0
T45 1673 1593 0 0

TlRegsAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1933986 0 0
T1 1960 1892 0 0
T2 1243 1191 0 0
T3 49501 49440 0 0
T4 1452 1389 0 0
T7 79422 79368 0 0
T17 16304 16253 0 0
T33 1831 1751 0 0
T34 1365 1301 0 0
T35 2481 2429 0 0
T45 1673 1593 0 0

TlRegsDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1933986 0 0
T1 1960 1892 0 0
T2 1243 1191 0 0
T3 49501 49440 0 0
T4 1452 1389 0 0
T7 79422 79368 0 0
T17 16304 16253 0 0
T33 1831 1751 0 0
T34 1365 1301 0 0
T35 2481 2429 0 0
T45 1673 1593 0 0

TlSbaAValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1933986 0 0
T1 1960 1892 0 0
T2 1243 1191 0 0
T3 49501 49440 0 0
T4 1452 1389 0 0
T7 79422 79368 0 0
T17 16304 16253 0 0
T33 1831 1751 0 0
T34 1365 1301 0 0
T35 2481 2429 0 0
T45 1673 1593 0 0

TlSbaDReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1948189 1933986 0 0
T1 1960 1892 0 0
T2 1243 1191 0 0
T3 49501 49440 0 0
T4 1452 1389 0 0
T7 79422 79368 0 0
T17 16304 16253 0 0
T33 1831 1751 0 0
T34 1365 1301 0 0
T35 2481 2429 0 0
T45 1673 1593 0 0

paramCheckNrHarts
NameAttemptsReal SuccessesFailuresIncomplete
Total 97 97 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T7 1 1 0 0
T17 1 1 0 0
T33 1 1 0 0
T34 1 1 0 0
T35 1 1 0 0
T45 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%