SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.96 | 90.91 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.96 | 90.91 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.96 | 90.91 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
76.96 | 90.91 | 61.70 | 87.54 | 57.14 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
57.78 | 80.39 | 38.89 | 57.14 | 62.50 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 582 | 582 | 0 | 0 |
OutputsKnown_A | 11689134 | 11603916 | 0 | 0 |
gen_flops.OutputDelay_A | 5844567 | 5800095 | 0 | 873 |
gen_no_flops.OutputDelay_A | 5844567 | 5801958 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 582 | 582 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T7 | 6 | 6 | 0 | 0 |
T17 | 6 | 6 | 0 | 0 |
T33 | 6 | 6 | 0 | 0 |
T34 | 6 | 6 | 0 | 0 |
T35 | 6 | 6 | 0 | 0 |
T45 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 11689134 | 11603916 | 0 | 0 |
T1 | 11760 | 11352 | 0 | 0 |
T2 | 7458 | 7146 | 0 | 0 |
T3 | 297006 | 296640 | 0 | 0 |
T4 | 8712 | 8334 | 0 | 0 |
T7 | 476532 | 476208 | 0 | 0 |
T17 | 97824 | 97518 | 0 | 0 |
T33 | 10986 | 10506 | 0 | 0 |
T34 | 8190 | 7806 | 0 | 0 |
T35 | 14886 | 14574 | 0 | 0 |
T45 | 10038 | 9558 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 5844567 | 5800095 | 0 | 873 |
T1 | 5880 | 5667 | 0 | 9 |
T2 | 3729 | 3564 | 0 | 9 |
T3 | 148503 | 148311 | 0 | 9 |
T4 | 4356 | 4158 | 0 | 9 |
T7 | 238266 | 238095 | 0 | 9 |
T17 | 48912 | 48750 | 0 | 9 |
T33 | 5493 | 5244 | 0 | 9 |
T34 | 4095 | 3894 | 0 | 9 |
T35 | 7443 | 7278 | 0 | 9 |
T45 | 5019 | 4770 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 5844567 | 5801958 | 0 | 0 |
T1 | 5880 | 5676 | 0 | 0 |
T2 | 3729 | 3573 | 0 | 0 |
T3 | 148503 | 148320 | 0 | 0 |
T4 | 4356 | 4167 | 0 | 0 |
T7 | 238266 | 238104 | 0 | 0 |
T17 | 48912 | 48759 | 0 | 0 |
T33 | 5493 | 5253 | 0 | 0 |
T34 | 4095 | 3903 | 0 | 0 |
T35 | 7443 | 7287 | 0 | 0 |
T45 | 5019 | 4779 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1948189 | 1933986 | 0 | 0 |
gen_flops.OutputDelay_A | 1948189 | 1933365 | 0 | 291 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933986 | 0 | 0 |
T1 | 1960 | 1892 | 0 | 0 |
T2 | 1243 | 1191 | 0 | 0 |
T3 | 49501 | 49440 | 0 | 0 |
T4 | 1452 | 1389 | 0 | 0 |
T7 | 79422 | 79368 | 0 | 0 |
T17 | 16304 | 16253 | 0 | 0 |
T33 | 1831 | 1751 | 0 | 0 |
T34 | 1365 | 1301 | 0 | 0 |
T35 | 2481 | 2429 | 0 | 0 |
T45 | 1673 | 1593 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933365 | 0 | 291 |
T1 | 1960 | 1889 | 0 | 3 |
T2 | 1243 | 1188 | 0 | 3 |
T3 | 49501 | 49437 | 0 | 3 |
T4 | 1452 | 1386 | 0 | 3 |
T7 | 79422 | 79365 | 0 | 3 |
T17 | 16304 | 16250 | 0 | 3 |
T33 | 1831 | 1748 | 0 | 3 |
T34 | 1365 | 1298 | 0 | 3 |
T35 | 2481 | 2426 | 0 | 3 |
T45 | 1673 | 1590 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1948189 | 1933986 | 0 | 0 |
gen_flops.OutputDelay_A | 1948189 | 1933365 | 0 | 291 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933986 | 0 | 0 |
T1 | 1960 | 1892 | 0 | 0 |
T2 | 1243 | 1191 | 0 | 0 |
T3 | 49501 | 49440 | 0 | 0 |
T4 | 1452 | 1389 | 0 | 0 |
T7 | 79422 | 79368 | 0 | 0 |
T17 | 16304 | 16253 | 0 | 0 |
T33 | 1831 | 1751 | 0 | 0 |
T34 | 1365 | 1301 | 0 | 0 |
T35 | 2481 | 2429 | 0 | 0 |
T45 | 1673 | 1593 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933365 | 0 | 291 |
T1 | 1960 | 1889 | 0 | 3 |
T2 | 1243 | 1188 | 0 | 3 |
T3 | 49501 | 49437 | 0 | 3 |
T4 | 1452 | 1386 | 0 | 3 |
T7 | 79422 | 79365 | 0 | 3 |
T17 | 16304 | 16250 | 0 | 3 |
T33 | 1831 | 1748 | 0 | 3 |
T34 | 1365 | 1298 | 0 | 3 |
T35 | 2481 | 2426 | 0 | 3 |
T45 | 1673 | 1590 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1948189 | 1933986 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1948189 | 1933986 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933986 | 0 | 0 |
T1 | 1960 | 1892 | 0 | 0 |
T2 | 1243 | 1191 | 0 | 0 |
T3 | 49501 | 49440 | 0 | 0 |
T4 | 1452 | 1389 | 0 | 0 |
T7 | 79422 | 79368 | 0 | 0 |
T17 | 16304 | 16253 | 0 | 0 |
T33 | 1831 | 1751 | 0 | 0 |
T34 | 1365 | 1301 | 0 | 0 |
T35 | 2481 | 2429 | 0 | 0 |
T45 | 1673 | 1593 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933986 | 0 | 0 |
T1 | 1960 | 1892 | 0 | 0 |
T2 | 1243 | 1191 | 0 | 0 |
T3 | 49501 | 49440 | 0 | 0 |
T4 | 1452 | 1389 | 0 | 0 |
T7 | 79422 | 79368 | 0 | 0 |
T17 | 16304 | 16253 | 0 | 0 |
T33 | 1831 | 1751 | 0 | 0 |
T34 | 1365 | 1301 | 0 | 0 |
T35 | 2481 | 2429 | 0 | 0 |
T45 | 1673 | 1593 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1948189 | 1933986 | 0 | 0 |
gen_flops.OutputDelay_A | 1948189 | 1933365 | 0 | 291 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933986 | 0 | 0 |
T1 | 1960 | 1892 | 0 | 0 |
T2 | 1243 | 1191 | 0 | 0 |
T3 | 49501 | 49440 | 0 | 0 |
T4 | 1452 | 1389 | 0 | 0 |
T7 | 79422 | 79368 | 0 | 0 |
T17 | 16304 | 16253 | 0 | 0 |
T33 | 1831 | 1751 | 0 | 0 |
T34 | 1365 | 1301 | 0 | 0 |
T35 | 2481 | 2429 | 0 | 0 |
T45 | 1673 | 1593 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933365 | 0 | 291 |
T1 | 1960 | 1889 | 0 | 3 |
T2 | 1243 | 1188 | 0 | 3 |
T3 | 49501 | 49437 | 0 | 3 |
T4 | 1452 | 1386 | 0 | 3 |
T7 | 79422 | 79365 | 0 | 3 |
T17 | 16304 | 16250 | 0 | 3 |
T33 | 1831 | 1748 | 0 | 3 |
T34 | 1365 | 1298 | 0 | 3 |
T35 | 2481 | 2426 | 0 | 3 |
T45 | 1673 | 1590 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1948189 | 1933986 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1948189 | 1933986 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933986 | 0 | 0 |
T1 | 1960 | 1892 | 0 | 0 |
T2 | 1243 | 1191 | 0 | 0 |
T3 | 49501 | 49440 | 0 | 0 |
T4 | 1452 | 1389 | 0 | 0 |
T7 | 79422 | 79368 | 0 | 0 |
T17 | 16304 | 16253 | 0 | 0 |
T33 | 1831 | 1751 | 0 | 0 |
T34 | 1365 | 1301 | 0 | 0 |
T35 | 2481 | 2429 | 0 | 0 |
T45 | 1673 | 1593 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933986 | 0 | 0 |
T1 | 1960 | 1892 | 0 | 0 |
T2 | 1243 | 1191 | 0 | 0 |
T3 | 49501 | 49440 | 0 | 0 |
T4 | 1452 | 1389 | 0 | 0 |
T7 | 79422 | 79368 | 0 | 0 |
T17 | 16304 | 16253 | 0 | 0 |
T33 | 1831 | 1751 | 0 | 0 |
T34 | 1365 | 1301 | 0 | 0 |
T35 | 2481 | 2429 | 0 | 0 |
T45 | 1673 | 1593 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 97 | 97 | 0 | 0 |
OutputsKnown_A | 1948189 | 1933986 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1948189 | 1933986 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 97 | 97 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
T33 | 1 | 1 | 0 | 0 |
T34 | 1 | 1 | 0 | 0 |
T35 | 1 | 1 | 0 | 0 |
T45 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933986 | 0 | 0 |
T1 | 1960 | 1892 | 0 | 0 |
T2 | 1243 | 1191 | 0 | 0 |
T3 | 49501 | 49440 | 0 | 0 |
T4 | 1452 | 1389 | 0 | 0 |
T7 | 79422 | 79368 | 0 | 0 |
T17 | 16304 | 16253 | 0 | 0 |
T33 | 1831 | 1751 | 0 | 0 |
T34 | 1365 | 1301 | 0 | 0 |
T35 | 2481 | 2429 | 0 | 0 |
T45 | 1673 | 1593 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1948189 | 1933986 | 0 | 0 |
T1 | 1960 | 1892 | 0 | 0 |
T2 | 1243 | 1191 | 0 | 0 |
T3 | 49501 | 49440 | 0 | 0 |
T4 | 1452 | 1389 | 0 | 0 |
T7 | 79422 | 79368 | 0 | 0 |
T17 | 16304 | 16253 | 0 | 0 |
T33 | 1831 | 1751 | 0 | 0 |
T34 | 1365 | 1301 | 0 | 0 |
T35 | 2481 | 2429 | 0 | 0 |
T45 | 1673 | 1593 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |