b938dde05c
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | rv_dm_smoke | 1.640s | 490.047us | 2 | 2 | 100.00 |
V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.990s | 186.064us | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 1.080s | 153.468us | 20 | 20 | 100.00 |
V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 6.720s | 6.154ms | 5 | 5 | 100.00 |
V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.130s | 154.117us | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 3.080s | 2.207ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 7.380s | 2.292ms | 20 | 20 | 100.00 |
V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 2.635m | 50.000ms | 4 | 5 | 80.00 |
V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 59.770s | 16.154ms | 5 | 5 | 100.00 |
V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 7.000s | 1.971ms | 2 | 2 | 100.00 |
V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 5.730s | 2.718ms | 2 | 2 | 100.00 |
V1 | cmderr_exception | rv_dm_cmderr_exception | 2.240s | 538.618us | 2 | 2 | 100.00 |
V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 2.100s | 495.045us | 2 | 2 | 100.00 |
V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.800s | 64.228us | 2 | 2 | 100.00 |
V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.150s | 959.206us | 2 | 2 | 100.00 |
V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.780s | 56.533us | 2 | 2 | 100.00 |
V1 | halt_resume | rv_dm_halt_resume_whereto | 0.790s | 45.346us | 0 | 2 | 0.00 |
V1 | progbuf_busy | rv_dm_progbuf_busy | 0.960s | 144.952us | 2 | 2 | 100.00 |
V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.750s | 81.740us | 2 | 2 | 100.00 |
V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 0.880s | 95.696us | 2 | 2 | 100.00 |
V1 | progbuf_exception | rv_dm_cmderr_exception | 2.240s | 538.618us | 2 | 2 | 100.00 |
V1 | rom_read_access | rv_dm_rom_read_access | 0.800s | 18.785us | 2 | 2 | 100.00 |
V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.510s | 113.412us | 5 | 5 | 100.00 |
V1 | csr_rw | rv_dm_csr_rw | 2.510s | 1.256ms | 20 | 20 | 100.00 |
V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.140m | 23.248ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | rv_dm_csr_aliasing | 1.128m | 1.174ms | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 9.870s | 3.923ms | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.128m | 1.174ms | 5 | 5 | 100.00 |
rv_dm_csr_rw | 2.510s | 1.256ms | 20 | 20 | 100.00 | ||
V1 | mem_walk | rv_dm_mem_walk | 0.700s | 57.861us | 5 | 5 | 100.00 |
V1 | mem_partial_access | rv_dm_mem_partial_access | 0.730s | 49.856us | 5 | 5 | 100.00 |
V1 | TOTAL | 158 | 161 | 98.14 | |||
V2 | idcode | rv_dm_smoke | 1.640s | 490.047us | 2 | 2 | 100.00 |
V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 1.080s | 229.097us | 2 | 2 | 100.00 |
V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 2.301m | 50.000ms | 0 | 2 | 0.00 |
V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0.990s | 99.371us | 2 | 2 | 100.00 |
V2 | sba | rv_dm_sba_tl_access | 1.330s | 163.996us | 0 | 20 | 0.00 |
rv_dm_delayed_resp_sba_tl_access | 1.410s | 576.776us | 0 | 20 | 0.00 | ||
V2 | bad_sba | rv_dm_bad_sba_tl_access | 1.310s | 177.630us | 0 | 20 | 0.00 |
V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 34.610s | 50.000ms | 0 | 20 | 0.00 |
V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.680s | 29.418us | 0 | 2 | 0.00 |
V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
V2 | ndmreset_req | rv_dm_ndmreset_req | 1.390s | 409.946us | 2 | 2 | 100.00 |
V2 | hart_unavail | rv_dm_hart_unavail | 0.850s | 58.944us | 5 | 5 | 100.00 |
V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 4.170s | 1.487ms | 1 | 1 | 100.00 |
rv_dm_tap_fsm_rand_reset | 36.870s | 11.030ms | 13 | 40 | 32.50 | ||
V2 | stress_all | rv_dm_stress_all | 16.260s | 4.838ms | 6 | 50 | 12.00 |
V2 | alert_test | rv_dm_alert_test | 0.780s | 18.684us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.660s | 294.507us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.660s | 294.507us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.128m | 1.174ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 2.510s | 113.412us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.510s | 1.256ms | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.170s | 416.771us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.128m | 1.174ms | 5 | 5 | 100.00 |
rv_dm_csr_hw_reset | 2.510s | 113.412us | 5 | 5 | 100.00 | ||
rv_dm_csr_rw | 2.510s | 1.256ms | 20 | 20 | 100.00 | ||
rv_dm_same_csr_outstanding | 8.170s | 416.771us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 121 | 276 | 43.84 | |||
V2S | tl_intg_err | rv_dm_sec_cm | 1.580s | 161.115us | 5 | 5 | 100.00 |
rv_dm_tl_intg_err | 20.200s | 4.473ms | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 12.920s | 2.936ms | 0 | 50 | 0.00 |
V3 | TOTAL | 0 | 50 | 0.00 | |||
TOTAL | 304 | 512 | 59.38 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 28 | 28 | 26 | 92.86 |
V2 | 18 | 16 | 8 | 44.44 |
V2S | 10 | 2 | 2 | 20.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
75.74 | 90.33 | 76.92 | 86.93 | 64.10 | 76.17 | 98.42 | 37.33 |
UVM_ERROR (rv_dm_scoreboard.sv:250) [scoreboard] Check failed sba_item.rdata[*] == data (* [*] vs * [*])
has 46 failures:
0.rv_dm_sba_tl_access.50384551408879925508964912497461215442453633033101869142046624120383624397102
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 42487285 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 15684 [0x3d44])
SBA item:
item: (sba_access_item@6553) { bus_op: BusOpRead size: SbaAccessSize16b addr: 'hee4db87a wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6501) { a_addr: 'hee4db878 a_data: 'h9eec0000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h2752f d_param: 'h0 d_source: 'h0 d_data: 'h3d442774 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd30 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
1.rv_dm_sba_tl_access.69233820928727874716786643828237032157351051990305206595271664676214204851947
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 71617320 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 50135 [0xc3d7])
SBA item:
item: (sba_access_item@6295) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'hbbfb67d6 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6205) { a_addr: 'hbbfb67d4 a_data: 'h16540000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h27943 d_param: 'h0 d_source: 'h0 d_data: 'hc3d72e0f d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd32 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 17 more failures.
0.rv_dm_delayed_resp_sba_tl_access.47971937010515679968884736131222766454141032958786229096964515019131626873698
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 12278284 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 472292850 [0x1c269df2])
SBA item:
item: (sba_access_item@5381) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'hef427d00 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5325) { a_addr: 'hef427d00 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h2412a d_param: 'h0 d_source: 'h0 d_data: 'h1c269df2 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd6b a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
3.rv_dm_delayed_resp_sba_tl_access.68686687454230716025624970213422740262734686909212547228083394425084029064782
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 44137096 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 2676041716 [0x9f8127f4])
SBA item:
item: (sba_access_item@5813) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h4b56ab50 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5775) { a_addr: 'h4b56ab50 a_data: 'h54b5d723 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h27444 d_param: 'h0 d_source: 'h0 d_data: 'h9f8127f4 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd6f a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 13 more failures.
2.rv_dm_bad_sba_tl_access.51940881007424930159063881914838768117337064777426006073272451109475897146801
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 80562189 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 6143719 [0x5dbee7])
SBA item:
item: (sba_access_item@5381) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'h6dac3069 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5325) { a_addr: 'h6dac3068 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h26b2a d_param: 'h0 d_source: 'h0 d_data: 'h5dbee786 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h1 d_user: 'hefa a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
3.rv_dm_bad_sba_tl_access.67888418689857023917885054046952644025898283492130416011401283991736985123670
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 36901282 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 2890649040 [0xac4bcdd0])
SBA item:
item: (sba_access_item@5933) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'ha3e57b00 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5877) { a_addr: 'ha3e57b00 a_data: 'h66d65e6 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h24ce8 d_param: 'h0 d_source: 'h0 d_data: 'hac4bcdd0 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'hec3 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 1 more failures.
2.rv_dm_autoincr_sba_tl_access.44159978936049574011812161283860837078061049647998021714636967036807390060103
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 17196448 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 2362727767 [0x8cd45d57])
SBA item:
item: (sba_access_item@5503) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'h0 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5413) { a_addr: 'h0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'h0 d_data: 'h8cd45d57 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd3c a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
3.rv_dm_autoincr_sba_tl_access.11272977759574402399177896487015558673844716667988331117769811347771123178205
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 107377665 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 788380157 [0x2efdb9fd])
SBA item:
item: (sba_access_item@5381) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h1aa7fdbc wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrBadAddr timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5325) { a_addr: 'h1aa7fdbc a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h265aa d_param: 'h0 d_source: 'h0 d_data: 'h2efdb9fd d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h0 d_user: 'hece a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 7 more failures.
UVM_ERROR (sba_access_monitor.sv:152) [m_sba_access_monitor] Check failed sberror ==
gmv(jtag_dmi_ral.sbcs.sberror) (* [] vs * [])` has 13 failures:
0.rv_dm_bad_sba_tl_access.76758704838419898512651050892175794222902764935660670519265783937418928892961
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 17746636 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 17746636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_bad_sba_tl_access.90954259284319705543954235141264872386763985420899270437281961887006595299442
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 53887710 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 53887710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
6.rv_dm_autoincr_sba_tl_access.44230406469711138143747241592262880341019329394935064850725262918158018081181
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 91468262 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 91468262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_dmi_monitor.sv:91) m_jtag_dmi_monitor [m_jtag_dmi_monitor] JTAG operation * != DmiOpNone in quiet period
has 12 failures:
Test rv_dm_halt_resume_whereto has 2 failures.
0.rv_dm_halt_resume_whereto.87392135105569345989565490190135062915251741853943872408093939144923703928803
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest/run.log
UVM_ERROR @ 34765327 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 34765327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_halt_resume_whereto.43468404969152894735323822444350660434678543359004795498944552950487094901978
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest/run.log
UVM_ERROR @ 45345691 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 45345691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 7 failures.
2.rv_dm_stress_all.22913819769079811330909257900268597258369872712869014183242728255134996602318
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1823425346 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 1823425346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_stress_all.82243603710326620418147227450210668964411332946111516040975298751580678654723
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 41232797 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 41232797 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test rv_dm_stress_all_with_rand_reset has 3 failures.
2.rv_dm_stress_all_with_rand_reset.28233241742384405285281284831075875820697166022411567462788020742766356813748
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28588786 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 28588786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.rv_dm_stress_all_with_rand_reset.79873545109384528587065857031117369062190915812010002145553749166743027266032
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/44.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 44075609 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 44075609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*])
has 12 failures:
Test rv_dm_jtag_dmi_debug_disabled has 2 failures.
0.rv_dm_jtag_dmi_debug_disabled.26006986436452299384750774982321177954580658880341929739621602306844255307561
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 29417901 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 866983077 [0x33ad1ca5])
UVM_INFO @ 29417901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dmi_debug_disabled.10043823131288439589651224946569519670215434607310438440816103446431877615131
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 12867984 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 1719281919 [0x667a28ff])
UVM_INFO @ 12867984 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 7 failures.
1.rv_dm_stress_all.5119527858962792295884841265281131709232708547038458958465802950779599137887
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1338531193 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (134104264 [0x7fe44c8] vs 3443221703 [0xcd3b64c7])
UVM_INFO @ 1338531193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_stress_all.70243203506260286073155296295556292887337133146307243178163848659037046366844
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 251480153 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 229294626 [0xdaac222])
UVM_INFO @ 251480153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test rv_dm_stress_all_with_rand_reset has 3 failures.
8.rv_dm_stress_all_with_rand_reset.8681027622936695447995371198667782511983385286610498693677779950631030941215
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 29754128 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (134104264 [0x7fe44c8] vs 130758765 [0x7cb386d])
UVM_INFO @ 29754128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_stress_all_with_rand_reset.29738794644108178437682273098794161197467374094290097869137617888579565334489
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 33025085 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (134104264 [0x7fe44c8] vs 2291607521 [0x889727e1])
UVM_INFO @ 33025085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*])
has 12 failures:
0.rv_dm_stress_all_with_rand_reset.63885051560979286728472468340090551864407415395443587304885844889353431550665
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 44403329 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 44403329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_stress_all_with_rand_reset.97032837414841618652592340414353179650062279107835164798112786616534381548034
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 81054866 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 81054866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
12.rv_dm_stress_all.100254117857038457268278828296929924386862782027640362946037003399022466116742
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 39132052 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 39132052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.rv_dm_stress_all.57993242662114929100672156246113059309495381411445680247844633031667167598732
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/16.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 17592575 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (4294443260 [0xfff800fc] vs 4209 [0x1071])
UVM_INFO @ 17592575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*])
has 11 failures:
0.rv_dm_tap_fsm_rand_reset.86882163076739854224085117603422767158159611961485105891640752127013282463103
Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 1947479306 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1947479306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_tap_fsm_rand_reset.56649612920876203338059489393019283682684871663119722735587883282861108555446
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 814619738 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 814619738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:136) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
has 9 failures:
3.rv_dm_stress_all_with_rand_reset.111564417266937283871190462208297940318510532073019505174472203053310407618317
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 47269137 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 47269137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_stress_all_with_rand_reset.79509003881195031373733317581795717934366226534660721177355190297657064082503
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 53891370 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 53891370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
13.rv_dm_stress_all.12997705876674596139954596274221787152880792041419386138365196941642080568270
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 16996002 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 16996002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_dm_stress_all.84359398628057035827654453945896441764273187283587282441628894438249833009774
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 6692808 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 6692808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[*].get_reset() (* [*] vs * [*])
has 8 failures:
4.rv_dm_stress_all.41975515795964020492803938757117983922349608824440365349521245552516870710078
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 4837584540 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (2958143569 [0xb051b051] vs 0 [0x0])
UVM_INFO @ 4837584540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
40.rv_dm_stress_all.6542650373315799155126337987612536403515852074822431159851771590492125882952
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 123889612 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (134104264 [0x7fe44c8] vs 0 [0x0])
UVM_INFO @ 123889612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
5.rv_dm_stress_all_with_rand_reset.63147026444792964195787907537074273932093644569527216194986298410689783131124
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 108226060 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (134104264 [0x7fe44c8] vs 0 [0x0])
UVM_INFO @ 108226060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all_with_rand_reset.90765856243048653893623743584664226090249284629867619131961941959018123552976
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 130897758 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (134104264 [0x7fe44c8] vs 0 [0x0])
UVM_INFO @ 130897758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*])
has 7 failures:
3.rv_dm_tap_fsm_rand_reset.29073181915701192217798616213060334351402754809733331833143448337917274691513
Line 279, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 2754490255 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2754490255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_tap_fsm_rand_reset.40349420767266032271732252447942719645881828308432980385761563289658662419202
Line 275, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 1732786949 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1732786949 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 7 failures:
9.rv_dm_stress_all_with_rand_reset.68378395333217707880070372086874883324124240159570615794880759147356389210722
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 36008499 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 36008499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_dm_stress_all_with_rand_reset.27176089057008855088950138556513621201834027289600311088662114948137101397935
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 318326130 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 318326130 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 6 failures:
0.rv_dm_stress_all.37681419227170314786044734703709700255277665167170529975661971321849203663631
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 34332419 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 34332419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_stress_all.82044354748081096250754658062016109895243663871066900433001486759717763479459
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 8260007 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 8260007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
11.rv_dm_stress_all_with_rand_reset.93597061409645878368343535634054810891688686571606380484633805990059696006882
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 62356010 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 62356010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.rv_dm_stress_all_with_rand_reset.5483057107899289588459678771818836729858607346513342902122501580650309200744
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20772704 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 20772704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:282) [scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (* [*] vs * [*])
has 5 failures:
Test rv_dm_autoincr_sba_tl_access has 2 failures.
1.rv_dm_autoincr_sba_tl_access.84959056039477105517750004398606003921746672050140311556298817387645419061710
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 104288551 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 104288551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_dm_autoincr_sba_tl_access.36786153478966379427380564689861128345704019099077298788423448190877300330308
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 72976800 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 72976800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_bad_sba_tl_access has 3 failures.
5.rv_dm_bad_sba_tl_access.99760336292650464702170015721935918253850685123977940834927443869254244659275
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 156970955 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 156970955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_bad_sba_tl_access.35943852381385281518700797870883232042012850071034821400902014757139628822962
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 81204543 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 81204543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 5 failures:
7.rv_dm_stress_all.18793926571811046512549714399457254094215958763958005590308581138737021792779
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 44875869 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 44875869 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.rv_dm_stress_all.39408590987390072143758673809518317240262762588579226707195997760023395856956
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 39320723 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 39320723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
26.rv_dm_stress_all_with_rand_reset.11486805921076492770977270805393894270230988635331897751653704005731828842033
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9193591 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 9193591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
30.rv_dm_stress_all_with_rand_reset.108453412871232077943897992797982894017891173381306648810375863967147246382198
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37196587 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 37196587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
has 4 failures:
Test rv_dm_jtag_dtm_idle_hint has 2 failures.
0.rv_dm_jtag_dtm_idle_hint.92399641837978583998305638169473273137789642084210558358215900735082316543416
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dtm_idle_hint.13345875488123803470175988336932409266716062241346910092021499423074448082954
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_jtag_dmi_csr_bit_bash has 1 failures.
4.rv_dm_jtag_dmi_csr_bit_bash.109885148811851091129113270832297108671116085084403657954357780149783311029592
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
17.rv_dm_autoincr_sba_tl_access.50591800961430084411789147910517346658121018951322938398171384791248339906855
Line 572, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*])
has 4 failures:
Test rv_dm_stress_all has 2 failures.
5.rv_dm_stress_all.50919565725662418071357240287471871717560852651268057917421158301218824016270
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 12245051 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 12245051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_stress_all.79065955898628090617021445154094113613708496810627909101347696901714248837428
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 13949373 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 13949373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
34.rv_dm_stress_all_with_rand_reset.29914799516526617852544666620774528464352696364270256334967515526265228784279
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 57981163 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 57981163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rv_dm_stress_all_with_rand_reset.115661158955289292461549158680560990929428676620799540818116459840618720958873
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 57286276 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 57286276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*])
has 4 failures:
Test rv_dm_stress_all has 2 failures.
8.rv_dm_stress_all.5698333926400935653051673286858519284954840776316616071374613588792396798572
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 74044089 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (28 [0x1c] vs 134104264 [0x7fe44c8])
UVM_INFO @ 74044089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rv_dm_stress_all.90595369972555955398228475127886952954793345497529043857494761109270864423571
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 16676040 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (9 [0x9] vs 134104264 [0x7fe44c8])
UVM_INFO @ 16676040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
10.rv_dm_stress_all_with_rand_reset.52407201954924337404964230268203193065875997994000550991508022971434023388179
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 75458756 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (22 [0x16] vs 134104264 [0x7fe44c8])
UVM_INFO @ 75458756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
46.rv_dm_stress_all_with_rand_reset.43752283752692942935616614456312902934676830997732456034613025050775940032121
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/46.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 88120751 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (7 [0x7] vs 134104264 [0x7fe44c8])
UVM_INFO @ 88120751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sba_access_monitor.sv:142) [m_sba_access_monitor] Check failed sbbusyerror ==
gmv(jtag_dmi_ral.sbcs.sbbusyerror) (* [] vs * [])` has 3 failures:
2.rv_dm_delayed_resp_sba_tl_access.26749177422342679280147739059328043417346848111111215064294235856000045215691
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 47975351 ps: (sba_access_monitor.sv:142) [uvm_test_top.env.m_sba_access_monitor] Check failed sbbusyerror == `gmv(jtag_dmi_ral.sbcs.sbbusyerror) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 47975351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_dm_delayed_resp_sba_tl_access.101860284692474251722099503687245667262849310538818922040028283737276727099117
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 97658604 ps: (sba_access_monitor.sv:142) [uvm_test_top.env.m_sba_access_monitor] Check failed sbbusyerror == `gmv(jtag_dmi_ral.sbcs.sbbusyerror) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 97658604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:59) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*])
has 3 failures:
4.rv_dm_tap_fsm_rand_reset.51660314360584074002940437737816642795220234366881773312016717234505355415987
Line 309, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 4603181577 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4603181577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.rv_dm_tap_fsm_rand_reset.61794967414249725394301768461623604288792164635732085036799351728023410399152
Line 307, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 10796228153 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10796228153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:275) [scoreboard] Check failed byte_mask == sba_tl_item.a_mask (* [*] vs * [*])
has 3 failures:
Test rv_dm_autoincr_sba_tl_access has 2 failures.
8.rv_dm_autoincr_sba_tl_access.39952741412802004441302300414721592699491160100025241562012664577083919184757
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 78258867 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (1 [0x1] vs 3 [0x3])
SBA item:
item: (sba_access_item@6397) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h45349e44 wdata: { [0]: 'hccf06d42 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6341) { a_addr: 'h45349e44 a_data: 'hccf06d42 a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h24203 d_param: 'h0 d_source: 'h0 d_data: 'hef4ed1bc d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1cac a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
10.rv_dm_autoincr_sba_tl_access.4126835361979200277225843813920578670982478491452708714947978694954009128903
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 100533369 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (4 [0x4] vs 12 [0xc])
SBA item:
item: (sba_access_item@5665) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hb31e9bbe wdata: { [0]: 'h217db5c6 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5609) { a_addr: 'hb31e9bbc a_data: 'hb5c60000 a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h279f8 d_param: 'h0 d_source: 'h0 d_data: 'h72b74451 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h1 d_user: 'h1c8c a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Test rv_dm_sba_tl_access has 1 failures.
15.rv_dm_sba_tl_access.102493220694776025250673931739820005648854507027240305067378094029721708051952
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 101617904 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (1 [0x1] vs 3 [0x3])
SBA item:
item: (sba_access_item@5933) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h468dd364 wdata: { [0]: 'he17c39c2 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5877) { a_addr: 'h468dd364 a_data: 'he17c39c2 a_mask: 'h3 a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h249ca d_param: 'h0 d_source: 'h0 d_data: 'h12788df2 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h1 d_user: 'h1cd6 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (rv_dm_scoreboard.sv:280) [scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (* [*] vs * [*])
has 3 failures:
Test rv_dm_bad_sba_tl_access has 2 failures.
9.rv_dm_bad_sba_tl_access.103985346606141237117835183118498067747000478098873777577029915005026378523120
Line 287, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 177629900 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 177629900 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_dm_bad_sba_tl_access.7733675488403257428415737779523152263152600583378076324967100316667564626771
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 108745403 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 108745403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
9.rv_dm_autoincr_sba_tl_access.83499834199554765090049612897069059077444237587098104556574987645025481689947
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 49184578 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 49184578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
has 3 failures:
21.rv_dm_tap_fsm_rand_reset.39727210404965361547401807998061883628611914431916085111348578798399631218934
Line 345, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 12029781065 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 12029781065 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.rv_dm_tap_fsm_rand_reset.4640331365418982080156686792295913212672373226851945861528603685843565701787
Line 297, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 6225460611 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 6225460611 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (jtag_dmi_monitor.sv:67) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: * dr_len: * ir: * dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: * ir_pause_count: * dr_pause_count: * }
has 3 failures:
Test rv_dm_stress_all_with_rand_reset has 2 failures.
29.rv_dm_stress_all_with_rand_reset.97782608589637549456757040546141635911600817485564941772759297401983754550640
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1139475 ps: (jtag_dmi_monitor.sv:67) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 1139475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
45.rv_dm_stress_all_with_rand_reset.67538829578653748332390794799783268391668151260055606983624701006262278924914
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/45.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2683960 ps: (jtag_dmi_monitor.sv:67) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 2683960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
37.rv_dm_stress_all.90805381754702007302203940661521062301556456040240526391663879568851346877656
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1186119 ps: (jtag_dmi_monitor.sv:67) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Bad packet: item: (jtag_item@5106) { ir_len: 'h0 dr_len: 'h0 ir: 'h0 dr: 'hxxxxxxxxxxxxxxxx dout: 'hxxxxxxxxxxxxxxxx bus_op: BusOpWrite skip_reselected_ir: 'h0 ir_pause_count: 'h0 dr_pause_count: 'h0 }
. ir_len & dr_len are both zero, or non-zero.
UVM_INFO @ 1186119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*])
has 2 failures:
6.rv_dm_stress_all_with_rand_reset.30550470644695912736818024055217134224470545628398714697704066719544323328278
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 343838800 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 343838800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.rv_dm_stress_all_with_rand_reset.47595400496243472212980836683717306420527542925693979102124211561174371804590
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 60645178 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 60645178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*)
has 2 failures:
13.rv_dm_tap_fsm_rand_reset.62502765656662683690526672445453323541835962015314026526986713724868902185221
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 5383903173 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 5383903173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rv_dm_tap_fsm_rand_reset.89065172112196250943560081360307428489781057109779892459140163910177182832751
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 2015036811 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 2015036811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_*
has 2 failures:
20.rv_dm_stress_all_with_rand_reset.88043473391906801050662127374979507246955265136301922537847720159229083608006
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 808211553 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1484011998 [0x587439de]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 808211553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.rv_dm_stress_all_with_rand_reset.2467666041993251664832949746421682297475806267196230573043260879195594103243
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 577791976 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 2457085923 [0x927427e3]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 577791976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*)
has 2 failures:
23.rv_dm_stress_all_with_rand_reset.46187156865469843331588055720594608609095796832757274672943747513855855570709
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 2936195414 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x6071b100)
UVM_INFO @ 2936195414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
36.rv_dm_stress_all_with_rand_reset.42165232126190273317726949459468789827869442302427927017763870914876339831562
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/36.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 4466782272 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xd7829100)
UVM_INFO @ 4466782272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:191) [rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*])
has 2 failures:
35.rv_dm_stress_all_with_rand_reset.72116264407422491539636979095868515422393047153010891781473966190780123782546
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 15791979 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 15791979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.rv_dm_stress_all_with_rand_reset.73183103082541303812289391649781808688672464441303869784077920521382302441501
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/39.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28291167 ps: (rv_dm_base_vseq.sv:191) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 28291167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:273) [scoreboard] Check failed data == act_data (* [*] vs * [*])
has 1 failures:
0.rv_dm_autoincr_sba_tl_access.9332397261324906901221419535225259186729644015079342840091817867866253717898
Line 278, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 135167064 ps: (rv_dm_scoreboard.sv:273) [uvm_test_top.env.scoreboard] Check failed data == act_data (7274496 [0x6f0000] vs 0 [0x0])
SBA item:
item: (sba_access_item@9969) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h917e540a wdata: { [0]: 'h38fd706f } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@9931) { a_addr: 'h917e5408 a_data: 'h6f000000 a_mask: 'h8 a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h27beb d_param: 'h0 d_source: 'h0 d_data: 'h31c4ab74 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1c80 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (rv_dm_scoreboard.sv:193) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5777) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * }
has 1 failures:
1.rv_dm_delayed_resp_sba_tl_access.16854753198592664946354361648515536939301763080376516085786563727519278733526
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 50894377 ps: (rv_dm_scoreboard.sv:193) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@5777) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h1d661bd2 wdata: { [0]: 'hdd878bb2 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 50894377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:260) [scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (* [*] vs * [*])
has 1 failures:
7.rv_dm_delayed_resp_sba_tl_access.108875435084268686213585306342761204928371613276443412003013974227209392327583
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 58811157 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (4 [0x4] vs 1 [0x1])
SBA item:
item: (sba_access_item@5821) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hbad6b373 wdata: { [0]: 'h45f1df57 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5665) { a_addr: 'hbad6b370 a_data: 'h49000000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h248f2 d_param: 'h0 d_source: 'h0 d_data: 'hee240c22 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd3b a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (sba_access_monitor.sv:173) [m_sba_access_monitor] Check failed (dmi_item.rdata inside {exp_addr, exp_addr + (* << size)})
has 1 failures:
7.rv_dm_autoincr_sba_tl_access.78180062260226797532302484014222816347137226028888798773365093353189637290563
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 222632700 ps: (sba_access_monitor.sv:173) [uvm_test_top.env.m_sba_access_monitor] Check failed (dmi_item.rdata inside {exp_addr, exp_addr + (1 << size)})
UVM_INFO @ 222632700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*])
has 1 failures:
10.rv_dm_stress_all.71460776316405344002904109504599093369444306145069402907353307363042130943808
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 18408746 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 18408746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_rv_debugger.sv:1108) [debugger] Check failed is_busy == * (* [*] vs * [*])
has 1 failures:
14.rv_dm_autoincr_sba_tl_access.77165326755254214378518452772263002434936513967262869524769331528375717061627
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 539381777 ps: (jtag_rv_debugger.sv:1108) [debugger] Check failed is_busy == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 539381777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sba_access_monitor.sv:178) [m_sba_access_monitor] Check failed dmi_item.rdata == exp_addr (* [*] vs * [*])
has 1 failures:
18.rv_dm_autoincr_sba_tl_access.8491373573044006393845338231981449505987266516145779041351176594971557536778
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 338458897 ps: (sba_access_monitor.sv:178) [uvm_test_top.env.m_sba_access_monitor] Check failed dmi_item.rdata == exp_addr (0 [0x0] vs 3478076760 [0xcf4f3d58])
UVM_INFO @ 338458897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:83) [scoreboard] Check failed rwdata == * (* [*] vs * [*])
has 1 failures:
19.rv_dm_stress_all.85458032656266017946987465503187359699718601105723639193909832343668611174786
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1153433007 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1153433007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*])
has 1 failures:
19.rv_dm_stress_all_with_rand_reset.36390141939705785599822147338929567561974440739771972762268480965735607058146
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 33880677 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 33880677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:54) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*])
has 1 failures:
23.rv_dm_stress_all.63539419023980131026277456936352187307345007232418835219451328697677334393065
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2198455137 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 2198455137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:43) [rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, rdata) (* [*] vs * [*])
has 1 failures:
25.rv_dm_stress_all.95309202102002355683991518090731230924550281114704310322456687662647493740456
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 33900816 ps: (rv_dm_ndmreset_req_vseq.sv:43) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 33900816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*])
has 1 failures:
28.rv_dm_stress_all.97917890716815126818689669049131205691284518926425678921360294915358475118386
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3605457320 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 3605457320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*])
has 1 failures:
29.rv_dm_tap_fsm_rand_reset.56000106761430965925515091030637199207935974144829327089159964386658805504177
Line 320, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 7447927338 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 7447927338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_idle_hint_vseq.sv:34) [rv_dm_jtag_dtm_idle_hint_vseq] Check failed * == get_field_val(jtag_dtm_ral.dtmcs.dmistat,rdata) (* [*] vs * [*])
has 1 failures:
43.rv_dm_stress_all.88536740317272006642259694850319958264706296025261901770369076810429142166513
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 45412697 ps: (rv_dm_jtag_dtm_idle_hint_vseq.sv:34) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_idle_hint_vseq] Check failed 0 == get_field_val(jtag_dtm_ral.dtmcs.dmistat,rdata) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 45412697 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:59) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*])
has 1 failures:
48.rv_dm_stress_all_with_rand_reset.69682448703931864121038874108418021405244517093884785372516058338214180097874
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/48.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 813713919 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 813713919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---