RV_DM Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.640s 1.222ms 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.910s 120.713us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.980s 109.690us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 7.190s 2.020ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.260s 216.125us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 3.350s 722.513us 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 3.460s 825.117us 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 40.240s 11.605ms 5 5 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 35.740s 39.048ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 10.550s 2.428ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 4.470s 2.053ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.300s 1.314ms 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 1.760s 531.112us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.820s 78.451us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 2.050s 449.491us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.810s 116.358us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 0.700s 15.327us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 1.400s 230.184us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.790s 59.022us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.830s 226.512us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.300s 1.314ms 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.820s 31.941us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.490s 272.359us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.520s 108.560us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.085m 19.593ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.200m 6.718ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 11.790s 5.556ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.200m 6.718ms 5 5 100.00
rv_dm_csr_rw 2.520s 108.560us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.770s 32.197us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.720s 17.945us 5 5 100.00
V1 TOTAL 159 161 98.76
V2 idcode rv_dm_smoke 1.640s 1.222ms 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.010s 372.921us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.138m 50.000ms 0 2 0.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.070s 293.799us 2 2 100.00
V2 sba rv_dm_sba_tl_access 1.630s 596.447us 1 20 5.00
rv_dm_delayed_resp_sba_tl_access 5.670s 3.484ms 2 20 10.00
V2 bad_sba rv_dm_bad_sba_tl_access 6.090s 6.035ms 2 20 10.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 1.810s 297.806us 0 20 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.800s 21.204us 0 2 0.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 2.540s 534.459us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 1.300s 175.906us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 3.960s 3.605ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 48.130s 15.404ms 11 40 27.50
V2 stress_all rv_dm_stress_all 19.340s 4.829ms 3 50 6.00
V2 alert_test rv_dm_alert_test 0.830s 19.099us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.950s 1.476ms 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.950s 1.476ms 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.200m 6.718ms 5 5 100.00
rv_dm_csr_hw_reset 2.490s 272.359us 5 5 100.00
rv_dm_csr_rw 2.520s 108.560us 20 20 100.00
rv_dm_same_csr_outstanding 8.300s 1.474ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.200m 6.718ms 5 5 100.00
rv_dm_csr_hw_reset 2.490s 272.359us 5 5 100.00
rv_dm_csr_rw 2.520s 108.560us 20 20 100.00
rv_dm_same_csr_outstanding 8.300s 1.474ms 20 20 100.00
V2 TOTAL 121 276 43.84
V2S tl_intg_err rv_dm_sec_cm 2.140s 387.517us 5 5 100.00
rv_dm_tl_intg_err 24.710s 3.819ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 6.524m 93.456ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 305 512 59.57

Testplan Progress

Items Total Written Passing Progress
V1 28 28 27 96.43
V2 18 16 8 44.44
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
79.17 93.86 81.18 87.61 73.08 82.33 98.52 37.60

Failure Buckets

Past Results