Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	204187	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	566422	1		T4	9		T16	30		T17	31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	487353	1		T16	20		T17	20		T13	2
values[0x0]	139570	1		T4	17		T16	6		T17	7
values[0x1]	143686	1		T4	25		T16	14		T17	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155810	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	614799	1		T4	13		T16	32		T17	31

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3300	1		T40	19		T43	26		T42	5
valid_sources[0x01]	3051	1		T4	1		T40	10		T43	17
valid_sources[0x02]	2960	1		T79	2		T40	18		T43	24
valid_sources[0x03]	2760	1		T129	1		T40	19		T43	29
valid_sources[0x04]	2728	1		T79	1		T15	1		T40	8
valid_sources[0x05]	3163	1		T79	2		T40	15		T43	30
valid_sources[0x06]	3102	1		T16	1		T40	18		T43	26
valid_sources[0x07]	3693	1		T17	1		T40	16		T43	22
valid_sources[0x08]	3123	1		T40	7		T43	12		T42	1
valid_sources[0x09]	3092	1		T78	1		T26	1		T40	13
valid_sources[0x0a]	2637	1		T17	2		T40	20		T43	25
valid_sources[0x0b]	3048	1		T4	1		T130	1		T15	1
valid_sources[0x0c]	3025	1		T40	16		T43	30		T42	4
valid_sources[0x0d]	3128	1		T13	1		T129	3		T131	6
valid_sources[0x0e]	2681	1		T16	1		T17	1		T21	1
valid_sources[0x0f]	3265	1		T40	17		T43	24		T65	3
valid_sources[0x10]	2991	1		T21	1		T79	1		T40	18
valid_sources[0x11]	2861	1		T17	2		T40	33		T43	31
valid_sources[0x12]	3211	1		T16	1		T40	21		T43	20
valid_sources[0x13]	2944	1		T11	6		T79	1		T40	32
valid_sources[0x14]	2578	1		T4	1		T131	3		T40	20
valid_sources[0x15]	2484	1		T40	19		T43	21		T41	3
valid_sources[0x16]	3113	1		T16	3		T15	2		T40	23
valid_sources[0x17]	2891	1		T13	1		T78	1		T40	10
valid_sources[0x18]	3266	1		T40	27		T43	18		T41	3
valid_sources[0x19]	2680	1		T69	1		T40	24		T43	34
valid_sources[0x1a]	3024	1		T13	2		T40	11		T43	17
valid_sources[0x1b]	2893	1		T4	1		T23	1		T40	22
valid_sources[0x1c]	4065	1		T17	3		T40	11		T43	32
valid_sources[0x1d]	3852	1		T4	1		T40	27		T43	39
valid_sources[0x1e]	2628	1		T16	1		T17	1		T79	1
valid_sources[0x1f]	3081	1		T79	2		T40	26		T43	23
valid_sources[0x20]	2495	1		T26	2		T40	31		T43	25
valid_sources[0x21]	2632	1		T17	1		T13	1		T79	1
valid_sources[0x22]	3350	1		T4	2		T23	2		T40	39
valid_sources[0x23]	2599	1		T79	1		T26	3		T131	2
valid_sources[0x24]	3070	1		T40	19		T43	19		T41	4
valid_sources[0x25]	2998	1		T78	1		T129	5		T40	27
valid_sources[0x26]	3282	1		T4	1		T17	2		T15	3
valid_sources[0x27]	2764	1		T4	1		T132	4		T79	1
valid_sources[0x28]	3033	1		T16	2		T17	1		T13	1
valid_sources[0x29]	3250	1		T4	1		T79	1		T40	18
valid_sources[0x2a]	2792	1		T40	32		T43	21		T41	9
valid_sources[0x2b]	3504	1		T40	14		T43	20		T41	2
valid_sources[0x2c]	2759	1		T4	1		T129	1		T21	1
valid_sources[0x2d]	2820	1		T40	19		T43	15		T42	1
valid_sources[0x2e]	3101	1		T5	11		T9	4		T40	24
valid_sources[0x2f]	3135	1		T9	3		T131	3		T40	14
valid_sources[0x30]	2976	1		T129	2		T40	16		T43	21
valid_sources[0x31]	2837	1		T16	1		T15	2		T40	12
valid_sources[0x32]	3034	1		T40	26		T43	27		T42	1
valid_sources[0x33]	2677	1		T17	1		T40	21		T43	20
valid_sources[0x34]	2607	1		T13	2		T21	1		T79	1
valid_sources[0x35]	3097	1		T40	5		T43	24		T42	5
valid_sources[0x36]	4022	1		T16	1		T40	41		T43	21
valid_sources[0x37]	3172	1		T40	7		T43	19		T41	5
valid_sources[0x38]	2799	1		T17	1		T15	1		T40	15
valid_sources[0x39]	2838	1		T40	25		T43	26		T42	5
valid_sources[0x3a]	3445	1		T40	6		T43	17		T42	5
valid_sources[0x3b]	2731	1		T23	2		T40	27		T43	29
valid_sources[0x3c]	3109	1		T4	1		T23	1		T40	17
valid_sources[0x3d]	2971	1		T4	1		T21	2		T79	1
valid_sources[0x3e]	3068	1		T4	2		T40	35		T43	15
valid_sources[0x3f]	2761	1		T13	1		T40	26		T43	18
valid_sources[0x40]	2882	1		T40	18		T43	27		T41	3
valid_sources[0x41]	2738	1		T13	2		T26	1		T40	23
valid_sources[0x42]	3308	1		T40	26		T43	17		T42	5
valid_sources[0x43]	2749	1		T4	1		T40	20		T43	32
valid_sources[0x44]	2927	1		T14	80		T23	2		T40	10
valid_sources[0x45]	2588	1		T79	1		T40	25		T43	21
valid_sources[0x46]	2851	1		T78	1		T40	12		T43	25
valid_sources[0x47]	2913	1		T131	1		T40	22		T43	18
valid_sources[0x48]	3659	1		T4	1		T17	2		T79	1
valid_sources[0x49]	3097	1		T4	1		T40	19		T43	26
valid_sources[0x4a]	3049	1		T17	1		T40	14		T43	27
valid_sources[0x4b]	2886	1		T40	16		T43	33		T41	8
valid_sources[0x4c]	2730	1		T13	1		T40	10		T43	30
valid_sources[0x4d]	3234	1		T4	1		T16	1		T40	23
valid_sources[0x4e]	2996	1		T17	1		T79	1		T26	1
valid_sources[0x4f]	2918	1		T4	1		T21	1		T40	18
valid_sources[0x50]	2834	1		T13	1		T40	19		T43	21
valid_sources[0x51]	2779	1		T15	2		T40	28		T43	25
valid_sources[0x52]	3410	1		T15	5		T40	26		T43	25
valid_sources[0x53]	2942	1		T4	1		T17	1		T79	1
valid_sources[0x54]	3535	1		T13	1		T79	2		T40	20
valid_sources[0x55]	3512	1		T40	25		T43	18		T41	10
valid_sources[0x56]	3202	1		T40	14		T43	30		T41	4
valid_sources[0x57]	4110	1		T79	1		T40	15		T43	24
valid_sources[0x58]	3429	1		T13	2		T40	17		T43	13
valid_sources[0x59]	3131	1		T5	24		T40	10		T43	29
valid_sources[0x5a]	3112	1		T4	1		T17	1		T69	2
valid_sources[0x5b]	3072	1		T16	1		T79	1		T15	5
valid_sources[0x5c]	3094	1		T40	42		T43	14		T41	10
valid_sources[0x5d]	2420	1		T16	2		T129	1		T15	1
valid_sources[0x5e]	2578	1		T9	2		T79	1		T40	29
valid_sources[0x5f]	2880	1		T21	3		T40	33		T43	30
valid_sources[0x60]	3209	1		T16	1		T17	1		T40	20
valid_sources[0x61]	3299	1		T21	2		T40	33		T43	26
valid_sources[0x62]	2631	1		T40	19		T43	29		T41	3
valid_sources[0x63]	3088	1		T40	14		T43	19		T41	2
valid_sources[0x64]	3217	1		T16	1		T10	33		T26	1
valid_sources[0x65]	2710	1		T25	1		T40	20		T43	17
valid_sources[0x66]	2913	1		T40	25		T43	15		T42	4
valid_sources[0x67]	2819	1		T4	1		T16	1		T79	1
valid_sources[0x68]	3007	1		T40	22		T43	21		T42	4
valid_sources[0x69]	2924	1		T17	1		T40	22		T43	36
valid_sources[0x6a]	3016	1		T16	1		T40	18		T43	33
valid_sources[0x6b]	2677	1		T15	1		T40	18		T43	14
valid_sources[0x6c]	2970	1		T40	8		T43	29		T42	2
valid_sources[0x6d]	2496	1		T40	20		T43	14		T42	3
valid_sources[0x6e]	2885	1		T40	27		T43	28		T42	2
valid_sources[0x6f]	2493	1		T40	15		T43	34		T42	4
valid_sources[0x70]	2806	1		T13	2		T21	1		T40	10
valid_sources[0x71]	3333	1		T21	1		T15	12		T40	33
valid_sources[0x72]	3121	1		T17	2		T40	14		T43	30
valid_sources[0x73]	3240	1		T40	25		T43	26		T41	4
valid_sources[0x74]	3191	1		T21	1		T79	1		T15	1
valid_sources[0x75]	2752	1		T40	26		T43	26		T41	15
valid_sources[0x76]	3157	1		T20	29		T21	1		T40	14
valid_sources[0x77]	2471	1		T13	2		T15	2		T40	35
valid_sources[0x78]	2769	1		T4	2		T21	1		T40	27
valid_sources[0x79]	3109	1		T40	26		T43	22		T42	1
valid_sources[0x7a]	2775	1		T40	34		T43	13		T42	1
valid_sources[0x7b]	2716	1		T17	1		T12	6		T131	6
valid_sources[0x7c]	2977	1		T4	2		T40	39		T43	27
valid_sources[0x7d]	2936	1		T69	1		T24	9		T40	28
valid_sources[0x7e]	3607	1		T4	1		T40	18		T43	27
valid_sources[0x7f]	2965	1		T15	1		T40	35		T43	23
valid_sources[0x80]	2856	1		T5	5		T40	27		T43	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

291349

1

T16

10

T17

11

T13

1

values[0x0]

all_enables

biggest_size

137827

1

T4

6

T16

6

T17

7

values[0x1]

all_enables

biggest_size

137246

1

T4

3

T16

14

T17

13

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4899	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	19176	1		T1	1		T27	1		T35	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9662	1		T40	36		T43	39		T41	21
values[0x0]	7098	1		T1	2		T3	1		T27	5
values[0x1]	7315	1		T1	9		T27	1		T35	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3767	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	20308	1		T1	4		T27	1		T35	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	99	1		T133	3		T134	1		T42	2
valid_sources[0x01]	58	1		T42	4		T112	1		T114	1
valid_sources[0x02]	74	1		T42	2		T83	7		T88	5
valid_sources[0x03]	91	1		T42	1		T65	1		T66	4
valid_sources[0x04]	101	1		T40	2		T42	3		T72	1
valid_sources[0x05]	81	1		T42	3		T65	1		T72	1
valid_sources[0x06]	72	1		T135	1		T42	2		T65	2
valid_sources[0x07]	146	1		T47	6		T136	1		T137	8
valid_sources[0x08]	117	1		T45	1		T138	9		T43	1
valid_sources[0x09]	83	1		T44	2		T42	5		T64	1
valid_sources[0x0a]	177	1		T139	1		T41	1		T42	2
valid_sources[0x0b]	95	1		T134	4		T65	1		T72	1
valid_sources[0x0c]	83	1		T46	1		T140	2		T42	5
valid_sources[0x0d]	74	1		T42	3		T65	1		T64	1
valid_sources[0x0e]	72	1		T65	1		T73	1		T82	2
valid_sources[0x0f]	101	1		T42	1		T65	4		T72	2
valid_sources[0x10]	95	1		T42	2		T64	2		T76	1
valid_sources[0x11]	110	1		T40	1		T42	3		T72	1
valid_sources[0x12]	65	1		T42	1		T65	1		T64	1
valid_sources[0x13]	88	1		T40	8		T42	2		T83	2
valid_sources[0x14]	74	1		T65	1		T73	2		T64	2
valid_sources[0x15]	88	1		T133	2		T42	3		T64	2
valid_sources[0x16]	64	1		T133	4		T42	3		T73	1
valid_sources[0x17]	66	1		T72	2		T64	2		T83	1
valid_sources[0x18]	66	1		T42	3		T65	1		T83	2
valid_sources[0x19]	142	1		T1	11		T117	3		T141	1
valid_sources[0x1a]	90	1		T65	2		T72	1		T73	1
valid_sources[0x1b]	92	1		T43	2		T42	5		T65	2
valid_sources[0x1c]	165	1		T39	1		T133	1		T65	1
valid_sources[0x1d]	90	1		T42	3		T83	6		T85	2
valid_sources[0x1e]	98	1		T39	1		T142	3		T42	4
valid_sources[0x1f]	77	1		T142	1		T43	4		T42	6
valid_sources[0x20]	88	1		T143	2		T42	4		T73	1
valid_sources[0x21]	67	1		T51	1		T42	1		T77	1
valid_sources[0x22]	99	1		T39	1		T42	3		T65	3
valid_sources[0x23]	87	1		T135	1		T42	5		T73	1
valid_sources[0x24]	95	1		T39	1		T45	1		T71	2
valid_sources[0x25]	126	1		T46	1		T135	4		T42	2
valid_sources[0x26]	111	1		T42	4		T74	1		T76	1
valid_sources[0x27]	78	1		T71	5		T42	3		T65	2
valid_sources[0x28]	87	1		T133	1		T139	1		T143	4
valid_sources[0x29]	107	1		T48	6		T42	2		T76	2
valid_sources[0x2a]	83	1		T142	1		T144	1		T42	3
valid_sources[0x2b]	85	1		T139	1		T42	6		T72	1
valid_sources[0x2c]	52	1		T142	1		T42	2		T65	1
valid_sources[0x2d]	111	1		T42	4		T76	2		T83	20
valid_sources[0x2e]	93	1		T39	1		T40	1		T42	2
valid_sources[0x2f]	69	1		T42	2		T66	1		T72	3
valid_sources[0x30]	112	1		T42	2		T72	2		T73	1
valid_sources[0x31]	180	1		T42	2		T66	2		T64	1
valid_sources[0x32]	74	1		T145	1		T65	1		T72	1
valid_sources[0x33]	87	1		T52	5		T42	1		T65	1
valid_sources[0x34]	72	1		T134	2		T72	4		T73	1
valid_sources[0x35]	114	1		T39	1		T42	2		T65	1
valid_sources[0x36]	68	1		T39	1		T42	4		T65	2
valid_sources[0x37]	71	1		T39	1		T146	1		T42	5
valid_sources[0x38]	100	1		T42	4		T72	2		T83	4
valid_sources[0x39]	92	1		T40	7		T42	7		T65	1
valid_sources[0x3a]	70	1		T42	3		T112	3		T114	1
valid_sources[0x3b]	106	1		T147	2		T139	1		T42	7
valid_sources[0x3c]	79	1		T148	2		T42	3		T72	2
valid_sources[0x3d]	109	1		T136	1		T42	5		T112	2
valid_sources[0x3e]	108	1		T45	1		T42	4		T83	1
valid_sources[0x3f]	105	1		T42	5		T64	1		T67	5
valid_sources[0x40]	150	1		T51	1		T147	1		T140	2
valid_sources[0x41]	102	1		T45	1		T139	1		T134	4
valid_sources[0x42]	56	1		T42	1		T65	2		T64	2
valid_sources[0x43]	90	1		T54	1		T42	3		T65	3
valid_sources[0x44]	85	1		T27	1		T142	1		T42	3
valid_sources[0x45]	92	1		T45	1		T149	9		T42	3
valid_sources[0x46]	67	1		T150	3		T141	1		T42	2
valid_sources[0x47]	83	1		T42	3		T80	1		T76	2
valid_sources[0x48]	105	1		T151	2		T42	3		T65	1
valid_sources[0x49]	91	1		T42	6		T72	1		T74	2
valid_sources[0x4a]	64	1		T42	1		T74	2		T64	2
valid_sources[0x4b]	85	1		T42	2		T65	1		T67	8
valid_sources[0x4c]	65	1		T152	2		T40	1		T42	5
valid_sources[0x4d]	92	1		T146	1		T136	1		T42	1
valid_sources[0x4e]	52	1		T139	1		T40	3		T42	2
valid_sources[0x4f]	72	1		T136	1		T42	1		T83	6
valid_sources[0x50]	86	1		T42	3		T72	3		T88	8
valid_sources[0x51]	112	1		T42	2		T65	1		T66	2
valid_sources[0x52]	73	1		T40	4		T42	1		T65	3
valid_sources[0x53]	114	1		T42	3		T74	2		T83	4
valid_sources[0x54]	87	1		T150	1		T42	2		T65	2
valid_sources[0x55]	153	1		T54	1		T42	2		T72	2
valid_sources[0x56]	142	1		T139	1		T42	5		T73	1
valid_sources[0x57]	79	1		T42	2		T114	1		T153	1
valid_sources[0x58]	143	1		T54	1		T42	1		T65	3
valid_sources[0x59]	133	1		T134	2		T154	8		T40	2
valid_sources[0x5a]	65	1		T42	1		T65	1		T74	2
valid_sources[0x5b]	81	1		T155	9		T42	3		T72	3
valid_sources[0x5c]	88	1		T42	1		T74	3		T83	7
valid_sources[0x5d]	107	1		T48	2		T42	5		T65	2
valid_sources[0x5e]	107	1		T42	4		T65	1		T74	1
valid_sources[0x5f]	74	1		T44	4		T142	1		T42	1
valid_sources[0x60]	87	1		T135	2		T42	3		T73	1
valid_sources[0x61]	85	1		T42	2		T81	1		T112	1
valid_sources[0x62]	69	1		T42	1		T65	3		T73	1
valid_sources[0x63]	90	1		T143	1		T82	2		T76	1
valid_sources[0x64]	79	1		T136	2		T42	3		T65	3
valid_sources[0x65]	67	1		T42	3		T72	2		T64	1
valid_sources[0x66]	90	1		T71	2		T72	3		T64	1
valid_sources[0x67]	93	1		T151	2		T42	3		T65	3
valid_sources[0x68]	79	1		T42	1		T72	1		T74	7
valid_sources[0x69]	165	1		T27	3		T52	2		T42	3
valid_sources[0x6a]	122	1		T156	12		T142	1		T42	4
valid_sources[0x6b]	86	1		T142	1		T42	2		T82	6
valid_sources[0x6c]	73	1		T151	1		T42	2		T112	6
valid_sources[0x6d]	110	1		T157	3		T158	3		T42	3
valid_sources[0x6e]	80	1		T42	4		T74	1		T114	1
valid_sources[0x6f]	99	1		T42	2		T72	1		T74	4
valid_sources[0x70]	180	1		T42	1		T66	1		T64	2
valid_sources[0x71]	107	1		T144	1		T135	2		T40	2
valid_sources[0x72]	71	1		T42	5		T74	1		T83	3
valid_sources[0x73]	78	1		T42	3		T65	3		T74	7
valid_sources[0x74]	142	1		T133	2		T42	5		T65	1
valid_sources[0x75]	113	1		T65	2		T80	1		T73	1
valid_sources[0x76]	52	1		T42	5		T81	1		T77	1
valid_sources[0x77]	63	1		T45	1		T133	1		T42	2
valid_sources[0x78]	69	1		T42	3		T73	1		T74	1
valid_sources[0x79]	113	1		T71	1		T42	1		T65	6
valid_sources[0x7a]	104	1		T39	1		T42	2		T72	1
valid_sources[0x7b]	141	1		T41	43		T65	1		T72	1
valid_sources[0x7c]	83	1		T42	9		T65	1		T72	2
valid_sources[0x7d]	66	1		T42	6		T65	1		T66	1
valid_sources[0x7e]	111	1		T134	3		T141	1		T40	5
valid_sources[0x7f]	83	1		T54	1		T117	1		T40	1
valid_sources[0x80]	104	1		T142	1		T43	4		T42	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6678

1

T40

14

T43

39

T41

19

values[0x0]

all_enables

biggest_size

6325

1

T1

1

T27

1

T35

2

values[0x1]

all_enables

biggest_size

6173

1

T45

3

T48

2

T71

1