SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 96.43 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 92.86 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
92.86 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 92.86 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 1 | 3 | 75.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 792314 | 1 | T4 | 42 | T16 | 40 | T17 | 40 | |||
auto[1] | 17555 | 1 | T14 | 80 | T15 | 80 | T40 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 1 | 3 | 75.00 |
NAME | COUNT | AT LEAST | NUMBER |
values[2] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 809678 | 1 | T4 | 42 | T16 | 40 | T17 | 40 | |||
values[1] | 14 | 1 | T40 | 1 | T120 | 1 | T61 | 1 | |||
values[3] | 106 | 1 | T40 | 5 | T66 | 2 | T73 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 809667 | 1 | T4 | 42 | T16 | 40 | T17 | 40 | |||
values[1] | 35 | 1 | T40 | 1 | T66 | 3 | T73 | 2 | |||
values[2] | 7 | 1 | T121 | 1 | T122 | 1 | T63 | 1 | |||
values[3] | 79 | 1 | T40 | 1 | T66 | 2 | T73 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 809569 | 1 | T4 | 42 | T16 | 40 | T17 | 40 | |||
auto[TlIntgErrCmd] | 98 | 1 | T40 | 3 | T66 | 3 | T73 | 3 | |||
auto[TlIntgErrData] | 109 | 1 | T40 | 2 | T66 | 5 | T73 | 4 | |||
auto[TlIntgErrBoth] | 93 | 1 | T40 | 5 | T66 | 2 | T73 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 39597 | 0 | T1 | 11 | T3 | 1 | T27 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 39402 | 1 | T1 | 11 | T3 | 1 | T27 | 6 | |||
values[1] | 12 | 1 | T40 | 1 | T66 | 1 | T123 | 1 | |||
values[2] | 4 | 1 | T121 | 1 | T62 | 1 | T124 | 1 | |||
values[3] | 113 | 1 | T40 | 4 | T66 | 4 | T73 | 4 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 39392 | 1 | T1 | 11 | T3 | 1 | T27 | 6 | |||
values[1] | 17 | 1 | T66 | 1 | T73 | 1 | T121 | 2 | |||
values[2] | 7 | 1 | T115 | 2 | T61 | 1 | T62 | 1 | |||
values[3] | 99 | 1 | T40 | 5 | T66 | 3 | T73 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 39297 | 1 | T1 | 11 | T3 | 1 | T27 | 6 | |||
auto[TlIntgErrCmd] | 95 | 1 | T40 | 4 | T66 | 3 | T73 | 3 | |||
auto[TlIntgErrData] | 105 | 1 | T40 | 5 | T66 | 4 | T73 | 4 | |||
auto[TlIntgErrBoth] | 100 | 1 | T40 | 1 | T66 | 3 | T73 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |