Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	241870	1		T4	33		T16	10		T17	9
full_word	567999	1		T4	9		T16	30		T17	31

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	809569	1		T4	42		T16	40		T17	40
auto[TlIntgErrCmd]	98	1		T40	3		T66	3		T73	3
auto[TlIntgErrData]	109	1		T40	2		T66	5		T73	4
auto[TlIntgErrBoth]	93	1		T40	5		T66	2		T73	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	489220	1		T16	20		T17	20		T13	2
auto[1]	320649	1		T4	42		T16	20		T17	20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	197553	1		T16	10		T17	9		T13	1
auto[TlIntgErrNone]	partial	auto[1]	44045	1		T4	33		T5	43		T6	16
auto[TlIntgErrNone]	full_word	auto[0]	291539	1		T16	10		T17	11		T13	1
auto[TlIntgErrNone]	full_word	auto[1]	276432	1		T4	9		T16	20		T17	20
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T66	2		T125	2		T115	3
auto[TlIntgErrCmd]	partial	auto[1]	47	1		T40	2		T66	1		T73	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T61	1		T123	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	8	1		T40	1		T62	2		T63	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T40	2		T66	3		T73	1
auto[TlIntgErrData]	partial	auto[1]	53	1		T66	1		T73	3		T125	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T66	1		T62	1		T63	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T126	1		T124	1		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T40	3		T66	2		T73	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T40	1		T73	2		T115	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T40	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1		T123	1		T124	1		T128	1