Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10
11CoveredT6,T10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9912676 9911850 0 0
selKnown1 10818366 10817540 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9912676 9911850 0 0
T1 322 320 0 0
T2 13914 13911 0 0
T3 471 468 0 0
T4 59913 59910 0 0
T5 4 6 0 0
T6 6 31 0 0
T7 2229 2226 0 0
T13 0 22 0 0
T16 32993 32990 0 0
T17 12 22 0 0
T27 315 312 0 0
T28 7 12 0 0
T31 4003 4000 0 0
T32 0 40 0 0
T33 0 40 0 0
T34 0 20 0 0
T35 383 380 0 0
T36 0 9 0 0
T37 5 9 0 0
T38 1 0 0 0
T39 311 308 0 0
T44 1 0 0 0
T45 1 0 0 0
T46 1 0 0 0
T48 1 0 0 0
T53 0 4 0 0
T68 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 10818366 10817540 0 0
T1 1243 1241 0 0
T2 13247 13245 0 0
T3 2075 2073 0 0
T4 143737 143735 0 0
T5 10 8 0 0
T6 12 10 0 0
T7 9530 9528 0 0
T13 0 6 0 0
T16 84211 84209 0 0
T17 8 6 0 0
T27 1408 1406 0 0
T28 14 12 0 0
T29 0 24 0 0
T31 7622 7620 0 0
T32 0 40 0 0
T33 0 40 0 0
T34 0 40 0 0
T35 1514 1512 0 0
T37 10 8 0 0
T38 2 0 0 0
T39 2082 2080 0 0
T45 2 0 0 0
T46 2 0 0 0
T48 2 0 0 0
T68 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10
11CoveredT6,T10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1164534 1164431 0 0
selKnown1 2070422 2070319 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1164534 1164431 0 0
T1 161 160 0 0
T2 6954 6953 0 0
T3 235 234 0 0
T4 29956 29955 0 0
T7 1114 1113 0 0
T16 16496 16495 0 0
T27 157 156 0 0
T31 2001 2000 0 0
T35 191 190 0 0
T39 155 154 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 2070422 2070319 0 0
T1 1082 1081 0 0
T2 6293 6292 0 0
T3 1840 1839 0 0
T4 113781 113780 0 0
T7 8416 8415 0 0
T16 67715 67714 0 0
T27 1251 1250 0 0
T31 5621 5620 0 0
T35 1323 1322 0 0
T39 1927 1926 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10
11CoveredT6,T10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 289 186 0 0
selKnown1 252 149 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 289 186 0 0
T5 4 3 0 0
T6 6 5 0 0
T13 0 11 0 0
T17 12 11 0 0
T28 7 6 0 0
T32 0 20 0 0
T33 0 20 0 0
T34 0 20 0 0
T36 0 9 0 0
T37 5 4 0 0
T38 1 0 0 0
T45 1 0 0 0
T46 1 0 0 0
T48 1 0 0 0
T68 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 252 149 0 0
T5 5 4 0 0
T6 6 5 0 0
T13 0 3 0 0
T17 4 3 0 0
T28 7 6 0 0
T29 0 12 0 0
T32 0 20 0 0
T33 0 20 0 0
T34 0 20 0 0
T37 5 4 0 0
T38 1 0 0 0
T45 1 0 0 0
T46 1 0 0 0
T48 1 0 0 0
T68 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10
11CoveredT6,T10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 8746237 8745927 0 0
selKnown1 8746237 8745927 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 8746237 8745927 0 0
T1 161 160 0 0
T2 6954 6953 0 0
T3 235 234 0 0
T4 29956 29955 0 0
T7 1114 1113 0 0
T16 16496 16495 0 0
T27 157 156 0 0
T31 2001 2000 0 0
T35 191 190 0 0
T39 155 154 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 8746237 8745927 0 0
T1 161 160 0 0
T2 6954 6953 0 0
T3 235 234 0 0
T4 29956 29955 0 0
T7 1114 1113 0 0
T16 16496 16495 0 0
T27 157 156 0 0
T31 2001 2000 0 0
T35 191 190 0 0
T39 155 154 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T10

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10
11CoveredT6,T10

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T10
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1616 1306 0 0
selKnown1 1455 1145 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1616 1306 0 0
T2 6 5 0 0
T3 1 0 0 0
T4 1 0 0 0
T5 0 3 0 0
T6 0 26 0 0
T7 1 0 0 0
T13 0 11 0 0
T16 1 0 0 0
T17 0 11 0 0
T27 1 0 0 0
T28 0 6 0 0
T31 1 0 0 0
T32 0 20 0 0
T33 0 20 0 0
T35 1 0 0 0
T37 0 5 0 0
T39 1 0 0 0
T44 1 0 0 0
T53 0 4 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1455 1145 0 0
T5 5 4 0 0
T6 6 5 0 0
T13 0 3 0 0
T17 4 3 0 0
T28 7 6 0 0
T29 0 12 0 0
T32 0 20 0 0
T33 0 20 0 0
T34 0 20 0 0
T37 5 4 0 0
T38 1 0 0 0
T45 1 0 0 0
T46 1 0 0 0
T48 1 0 0 0
T68 1 0 0 0

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