Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk	60.00			60.00
tb.dut.u_reg_regs.u_chk.u_chk	89.23			89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	89.23			89.23

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00			60.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.00			60.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T2,*T3,*T27	Yes	T3,T27,T4	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T27	Yes	T1,T3,T27	INPUT
data_o[56:0]	Yes	Yes	T2,T3,T27	Yes	T3,T27,T4	OUTPUT
syndrome_o[6:0]	Yes	Yes	T3,T16,T35	Yes	T2,T3,T27	OUTPUT
err_o[1:0]	Yes	Yes	T3,T4,T16	Yes	T3,T16,T35	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	260	156	60.00
Total Bits 0->1	130	78	60.00
Total Bits 1->0	130	78	60.00

Ports	4	2	50.00
Port Bits	260	156	60.00
Port Bits 0->1	130	78	60.00
Port Bits 1->0	130	78	60.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[5:0]	Yes	Yes	*T27,*T5,*T48	Yes	T5,T28,T37	INPUT
data_i[56:6]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T5,T28,T33	Yes	T27,T35,T5	INPUT
data_o[24:0]	Yes	Yes	*T27,*T5,*T48	Yes	T5,T28,T37	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[56:26]	Yes	Yes	T61,T62,T63	Yes	T61,T62,T63	OUTPUT
syndrome_o[6:0]	Yes	Yes	T5,T28,T37	Yes	T35,T5,T45	OUTPUT
err_o[1:0]	Yes	Yes	T5,T28,T37	Yes	T35,T5,T45	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T2,*T3,*T7	Yes	T3,T35,T5	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T27	Yes	T1,T3,T27	INPUT
data_o[56:0]	Yes	Yes	T2,T3,T7	Yes	T3,T35,T5	OUTPUT
syndrome_o[6:0]	Yes	Yes	T3,T35,T5	Yes	T2,T3,T35	OUTPUT
err_o[1:0]	Yes	Yes	T3,T35,T5	Yes	T3,T35,T5	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T16,*T17,*T5	Yes	T27,T4,T16	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T4,T16,T17	Yes	T4,T16,T17	INPUT
data_o[56:0]	Yes	Yes	T16,T17,T5	Yes	T27,T4,T16	OUTPUT
syndrome_o[6:0]	Yes	Yes	T16,T37,T13	Yes	T27,T16,T45	OUTPUT
err_o[1:0]	Yes	Yes	T4,T16,T39	Yes	T16,T17,T5	OUTPUT

*Tests covering at least one bit in the range