SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.rv_dm_regs_csr_assert | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
no children |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
TlulOOBAddrErr_A | 33109374 | 14503 | 0 | 0 |
late_debug_enable_rd_A | 33109374 | 2075 | 0 | 0 |
late_debug_enable_regwen_rd_A | 33109374 | 2968 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 33109374 | 14503 | 0 | 0 |
T28 | 26263 | 3 | 0 | 0 |
T29 | 19607 | 2 | 0 | 0 |
T30 | 7883 | 19 | 0 | 0 |
T31 | 19862 | 612 | 0 | 0 |
T66 | 9703 | 369 | 0 | 0 |
T67 | 6729 | 407 | 0 | 0 |
T68 | 5752 | 216 | 0 | 0 |
T69 | 7398 | 110 | 0 | 0 |
T70 | 8670 | 585 | 0 | 0 |
T71 | 81209 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 33109374 | 2075 | 0 | 0 |
T25 | 5018 | 4 | 0 | 0 |
T31 | 19862 | 59 | 0 | 0 |
T58 | 20389 | 18 | 0 | 0 |
T61 | 8950 | 9 | 0 | 0 |
T62 | 782066 | 70 | 0 | 0 |
T77 | 21953 | 27 | 0 | 0 |
T82 | 202379 | 24 | 0 | 0 |
T104 | 163547 | 71 | 0 | 0 |
T105 | 291282 | 15 | 0 | 0 |
T106 | 104606 | 77 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 33109374 | 2968 | 0 | 0 |
T25 | 5018 | 8 | 0 | 0 |
T31 | 19862 | 49 | 0 | 0 |
T58 | 20389 | 31 | 0 | 0 |
T62 | 782066 | 113 | 0 | 0 |
T75 | 197761 | 1016 | 0 | 0 |
T77 | 21953 | 9 | 0 | 0 |
T82 | 202379 | 29 | 0 | 0 |
T104 | 163547 | 81 | 0 | 0 |
T105 | 291282 | 15 | 0 | 0 |
T106 | 104606 | 91 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |