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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
 dap 85.53 98.68 93.42 66.00 94.57 75.00
gen_alert_tx[0].u_prim_alert_sender 83.33 83.33
 i_tlul_adapter_reg 93.27 99.00 80.90 93.33 93.10 100.00
rv_dm_regs_csr_assert 100.00 100.00
 tl_adapter_host_sba 85.66 97.67 77.78 72.86 80.00 100.00
tlul_assert_device_mem 95.24 100.00 85.71 100.00
tlul_assert_device_regs 95.24 100.00 85.71 100.00
tlul_assert_host_sba 64.34 53.33 42.86 96.83
 u_dm_top 65.60 75.80 52.85 42.86 56.50 100.00
 u_lc_en_sync_copies 100.00 100.00 100.00
 u_pm_en_sync 100.00 100.00 100.00 100.00
 u_prim_clock_mux2 100.00 100.00 100.00 100.00
 u_prim_flop_2sync_lc_rst_assert 100.00 100.00 100.00
 u_prim_flop_2sync_lc_rst_sync 100.00 100.00 100.00
 u_prim_lc_sync_lc_dft_en 100.00 100.00 100.00 100.00
 u_prim_lc_sync_lc_hw_debug_en 100.00 100.00 100.00 100.00
 u_prim_mubi32_sync_late_debug_enable 100.00 100.00 100.00
 u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00 100.00
 u_prim_rst_n_mux2 100.00 100.00 100.00 100.00
 u_reg_regs 98.19 98.69 98.71 93.55 100.00 100.00
 u_tlul_lc_gate_rom 79.72 93.70 67.86 71.43 78.12 87.50
 u_tlul_lc_gate_sba 59.17 84.25 39.29 28.57 56.25 87.50