Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T10,T8

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10,T8
11CoveredT6,T10,T8

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T10,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 11274513 11273811 0 0
selKnown1 12566309 12565607 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 11274513 11273811 0 0
T1 310 308 0 0
T2 306 304 0 0
T3 348 346 0 0
T4 388 386 0 0
T5 306 304 0 0
T6 17 15 0 0
T8 0 11 0 0
T9 14 12 0 0
T10 15 13 0 0
T12 1584 1582 0 0
T13 306 304 0 0
T14 382 380 0 0
T16 340 338 0 0
T17 310 308 0 0
T18 42 40 0 0
T19 0 20 0 0
T20 0 20 0 0
T21 0 24 0 0
T23 0 9 0 0
T26 0 18 0 0
T27 2 0 0 0
T41 2 0 0 0
T42 2 0 0 0
T48 2 0 0 0
T49 2 0 0 0
T50 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 12566309 12565607 0 0
T1 1341 1339 0 0
T2 1563 1561 0 0
T3 2073 2071 0 0
T4 1475 1473 0 0
T5 2050 2048 0 0
T6 6 4 0 0
T8 0 10 0 0
T9 14 12 0 0
T10 8 6 0 0
T12 2699 2697 0 0
T13 1933 1931 0 0
T14 1330 1328 0 0
T16 2198 2196 0 0
T17 3384 3382 0 0
T18 42 40 0 0
T19 0 20 0 0
T20 0 20 0 0
T21 0 6 0 0
T23 0 8 0 0
T26 0 6 0 0
T27 2 0 0 0
T41 2 0 0 0
T42 2 0 0 0
T48 2 0 0 0
T49 2 0 0 0
T50 2 0 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T10,T8

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10,T8
11CoveredT6,T10,T8

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T21
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 439082 439012 0 0
selKnown1 1731033 1730963 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 439082 439012 0 0
T1 155 154 0 0
T2 153 152 0 0
T3 174 173 0 0
T4 194 193 0 0
T5 153 152 0 0
T12 792 791 0 0
T13 153 152 0 0
T14 191 190 0 0
T16 170 169 0 0
T17 155 154 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1731033 1730963 0 0
T1 1186 1185 0 0
T2 1410 1409 0 0
T3 1899 1898 0 0
T4 1281 1280 0 0
T5 1897 1896 0 0
T12 1907 1906 0 0
T13 1780 1779 0 0
T14 1139 1138 0 0
T16 2028 2027 0 0
T17 3229 3228 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T10,T8

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10,T8
11CoveredT6,T10,T8

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T21
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 188 118 0 0
selKnown1 181 111 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 188 118 0 0
T6 3 2 0 0
T8 0 5 0 0
T9 7 6 0 0
T10 4 3 0 0
T18 21 20 0 0
T19 0 10 0 0
T20 0 10 0 0
T21 0 4 0 0
T23 0 4 0 0
T26 0 9 0 0
T27 1 0 0 0
T41 1 0 0 0
T42 1 0 0 0
T48 1 0 0 0
T49 1 0 0 0
T50 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 181 111 0 0
T6 3 2 0 0
T8 0 5 0 0
T9 7 6 0 0
T10 4 3 0 0
T18 21 20 0 0
T19 0 10 0 0
T20 0 10 0 0
T21 0 3 0 0
T23 0 4 0 0
T26 0 3 0 0
T27 1 0 0 0
T41 1 0 0 0
T42 1 0 0 0
T48 1 0 0 0
T49 1 0 0 0
T50 1 0 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T10,T8

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10,T8
11CoveredT6,T10,T8

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T10,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10833613 10833332 0 0
selKnown1 10833613 10833332 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10833613 10833332 0 0
T1 155 154 0 0
T2 153 152 0 0
T3 174 173 0 0
T4 194 193 0 0
T5 153 152 0 0
T12 792 791 0 0
T13 153 152 0 0
T14 191 190 0 0
T16 170 169 0 0
T17 155 154 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 10833613 10833332 0 0
T1 155 154 0 0
T2 153 152 0 0
T3 174 173 0 0
T4 194 193 0 0
T5 153 152 0 0
T12 792 791 0 0
T13 153 152 0 0
T14 191 190 0 0
T16 170 169 0 0
T17 155 154 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT6,T10,T8

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T10,T8
11CoveredT6,T10,T8

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT6,T10,T8
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1630 1349 0 0
selKnown1 1482 1201 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1630 1349 0 0
T6 14 13 0 0
T8 0 6 0 0
T9 7 6 0 0
T10 11 10 0 0
T18 21 20 0 0
T19 0 10 0 0
T20 0 10 0 0
T21 0 20 0 0
T23 0 5 0 0
T26 0 9 0 0
T27 1 0 0 0
T41 1 0 0 0
T42 1 0 0 0
T48 1 0 0 0
T49 1 0 0 0
T50 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1482 1201 0 0
T6 3 2 0 0
T8 0 5 0 0
T9 7 6 0 0
T10 4 3 0 0
T18 21 20 0 0
T19 0 10 0 0
T20 0 10 0 0
T21 0 3 0 0
T23 0 4 0 0
T26 0 3 0 0
T27 1 0 0 0
T41 1 0 0 0
T42 1 0 0 0
T48 1 0 0 0
T49 1 0 0 0
T50 1 0 0 0

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