SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
47.72 | 72.55 | 33.33 | 28.57 | 54.17 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
75.72 | 96.08 | 77.78 | 71.43 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 420 | 420 | 0 | 0 |
OutputsKnown_A | 10386198 | 10312962 | 0 | 0 |
gen_flops.OutputDelay_A | 5193099 | 5154852 | 0 | 630 |
gen_no_flops.OutputDelay_A | 5193099 | 5156481 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 420 | 420 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T12 | 6 | 6 | 0 | 0 |
T13 | 6 | 6 | 0 | 0 |
T14 | 6 | 6 | 0 | 0 |
T16 | 6 | 6 | 0 | 0 |
T17 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 10386198 | 10312962 | 0 | 0 |
T1 | 7116 | 6570 | 0 | 0 |
T2 | 8460 | 8136 | 0 | 0 |
T3 | 11394 | 11076 | 0 | 0 |
T4 | 7686 | 7332 | 0 | 0 |
T5 | 11382 | 10830 | 0 | 0 |
T12 | 11442 | 11016 | 0 | 0 |
T13 | 10680 | 10122 | 0 | 0 |
T14 | 6834 | 6444 | 0 | 0 |
T16 | 12168 | 11670 | 0 | 0 |
T17 | 19374 | 18936 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 5193099 | 5154852 | 0 | 630 |
T1 | 3558 | 3276 | 0 | 9 |
T2 | 4230 | 4059 | 0 | 9 |
T3 | 5697 | 5529 | 0 | 9 |
T4 | 3843 | 3657 | 0 | 9 |
T5 | 5691 | 5406 | 0 | 9 |
T12 | 5721 | 5499 | 0 | 9 |
T13 | 5340 | 5052 | 0 | 9 |
T14 | 3417 | 3213 | 0 | 9 |
T16 | 6084 | 5826 | 0 | 9 |
T17 | 9687 | 9459 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 5193099 | 5156481 | 0 | 0 |
T1 | 3558 | 3285 | 0 | 0 |
T2 | 4230 | 4068 | 0 | 0 |
T3 | 5697 | 5538 | 0 | 0 |
T4 | 3843 | 3666 | 0 | 0 |
T5 | 5691 | 5415 | 0 | 0 |
T12 | 5721 | 5508 | 0 | 0 |
T13 | 5340 | 5061 | 0 | 0 |
T14 | 3417 | 3222 | 0 | 0 |
T16 | 6084 | 5835 | 0 | 0 |
T17 | 9687 | 9468 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1731033 | 1718827 | 0 | 0 |
gen_flops.OutputDelay_A | 1731033 | 1718284 | 0 | 210 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718284 | 0 | 210 |
T1 | 1186 | 1092 | 0 | 3 |
T2 | 1410 | 1353 | 0 | 3 |
T3 | 1899 | 1843 | 0 | 3 |
T4 | 1281 | 1219 | 0 | 3 |
T5 | 1897 | 1802 | 0 | 3 |
T12 | 1907 | 1833 | 0 | 3 |
T13 | 1780 | 1684 | 0 | 3 |
T14 | 1139 | 1071 | 0 | 3 |
T16 | 2028 | 1942 | 0 | 3 |
T17 | 3229 | 3153 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1731033 | 1718827 | 0 | 0 |
gen_flops.OutputDelay_A | 1731033 | 1718284 | 0 | 210 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718284 | 0 | 210 |
T1 | 1186 | 1092 | 0 | 3 |
T2 | 1410 | 1353 | 0 | 3 |
T3 | 1899 | 1843 | 0 | 3 |
T4 | 1281 | 1219 | 0 | 3 |
T5 | 1897 | 1802 | 0 | 3 |
T12 | 1907 | 1833 | 0 | 3 |
T13 | 1780 | 1684 | 0 | 3 |
T14 | 1139 | 1071 | 0 | 3 |
T16 | 2028 | 1942 | 0 | 3 |
T17 | 3229 | 3153 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1731033 | 1718827 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1731033 | 1718827 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1731033 | 1718827 | 0 | 0 |
gen_flops.OutputDelay_A | 1731033 | 1718284 | 0 | 210 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718284 | 0 | 210 |
T1 | 1186 | 1092 | 0 | 3 |
T2 | 1410 | 1353 | 0 | 3 |
T3 | 1899 | 1843 | 0 | 3 |
T4 | 1281 | 1219 | 0 | 3 |
T5 | 1897 | 1802 | 0 | 3 |
T12 | 1907 | 1833 | 0 | 3 |
T13 | 1780 | 1684 | 0 | 3 |
T14 | 1139 | 1071 | 0 | 3 |
T16 | 2028 | 1942 | 0 | 3 |
T17 | 3229 | 3153 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1731033 | 1718827 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1731033 | 1718827 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70 | 70 | 0 | 0 |
OutputsKnown_A | 1731033 | 1718827 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1731033 | 1718827 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70 | 70 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T17 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1731033 | 1718827 | 0 | 0 |
T1 | 1186 | 1095 | 0 | 0 |
T2 | 1410 | 1356 | 0 | 0 |
T3 | 1899 | 1846 | 0 | 0 |
T4 | 1281 | 1222 | 0 | 0 |
T5 | 1897 | 1805 | 0 | 0 |
T12 | 1907 | 1836 | 0 | 0 |
T13 | 1780 | 1687 | 0 | 0 |
T14 | 1139 | 1074 | 0 | 0 |
T16 | 2028 | 1945 | 0 | 0 |
T17 | 3229 | 3156 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |