Module Definition
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Module : debug_rom
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 100.00 100.00 83.33

Source File(s) :
/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_dm_top.i_dm_mem.gen_rom_snd_scratch.i_debug_rom 94.44 100.00 100.00 83.33



Module Instance : tb.dut.u_dm_top.i_dm_mem.gen_rom_snd_scratch.i_debug_rom

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 100.00 100.00 83.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 100.00 100.00 83.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
75.45 78.95 51.61 100.00 71.25 i_dm_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : debug_rom
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN5311100.00
ALWAYS5633100.00
ALWAYS6633100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
53 1 1
56 1 1
57 1 1
59 1 1
66 1 1
67 1 1
68 1 1
==> MISSING_ELSE


Cond Coverage for Module : debug_rom
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       53
 EXPRESSION (req_i ? addr_i[(($clog2(RomSize) - 1) + 3):3] : addr_q)
             --1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T13,T6

Branch Coverage for Module : debug_rom
Line No.TotalCoveredPercent
Branches 6 5 83.33
TERNARY 53 2 2 100.00
IF 56 2 2 100.00
IF 67 2 1 50.00

WARNING: The source file /workspace/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv' or '../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 53 (req_i) ?

Branches:
-1-StatusTests
1 Covered T5,T13,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 56 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 67 if ((addr_q < 5'(RomSize)))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%