Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk	56.15			56.15
tb.dut.u_reg_regs.u_chk.u_chk	89.23			89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	89.23			89.23

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.15			56.15

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
56.15			56.15

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T3,*T4,*T14	Yes	T4,T16,T6	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T3,T4,T14	Yes	T4,T16,T6	OUTPUT
syndrome_o[6:0]	Yes	Yes	T4,T13,T6	Yes	T3,T4,T13	OUTPUT
err_o[1:0]	Yes	Yes	T2,T4,T6	Yes	T1,T3,T4	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	260	146	56.15
Total Bits 0->1	130	75	57.69
Total Bits 1->0	130	71	54.62

Ports	4	2	50.00
Port Bits	260	146	56.15
Port Bits 0->1	130	75	57.69
Port Bits 1->0	130	71	54.62

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	*T3,*T14,T18	Yes	T18,T8,T28	INPUT
data_i[56:4]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T18,T8,T28	Yes	T1,T14,T17	INPUT
data_o[3:0]	Yes	Yes	*T3,*T14,T18	Yes	T18,T8,T28	OUTPUT
data_o[4]	No	No		Yes	T8	OUTPUT
data_o[6:5]	Yes	Yes	T52,*T8,*T28	Yes	T52,T8,T28	OUTPUT
data_o[7]	No	No		No		OUTPUT
data_o[22:8]	Yes	Yes	*T53,*T54,*T55	Yes	T56,T53,T57	OUTPUT
data_o[23]	No	No		Yes	T1,T58	OUTPUT
data_o[34:24]	Yes	Yes	*T18,*T28,*T53	Yes	T18,T14,T28	OUTPUT
data_o[35]	No	No		Yes	T59	OUTPUT
data_o[37:36]	Yes	Yes	T52,*T57	Yes	T52,T57	OUTPUT
data_o[38]	No	No		No		OUTPUT
data_o[39]	Yes	Yes	*T52,*T57	Yes	T52,T57	OUTPUT
data_o[40]	No	No		Yes	T60	OUTPUT
data_o[56:41]	Yes	Yes	T8,T61,T28	Yes	T7,T8,T61	OUTPUT
syndrome_o[6:0]	Yes	Yes	T18,T8,T28	Yes	T3,T27,T41	OUTPUT
err_o[1:0]	Yes	Yes	T18,T8,T28	Yes	T1,T3,T14	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T4,*T6,*T27	Yes	T4,T6,T27	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T4,T6,T27	Yes	T4,T6,T27	OUTPUT
syndrome_o[6:0]	Yes	Yes	T4,T6,T27	Yes	T4,T27,T9	OUTPUT
err_o[1:0]	Yes	Yes	T4,T6,T27	Yes	T4,T6,T27	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T13,*T6,*T9	Yes	T16,T14,T5	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T5,T13,T6	Yes	T5,T13,T6	INPUT
data_o[56:0]	Yes	Yes	T13,T6,T9	Yes	T16,T14,T5	OUTPUT
syndrome_o[6:0]	Yes	Yes	T13,T9,T18	Yes	T13,T9,T18	OUTPUT
err_o[1:0]	Yes	Yes	T2,T14,T5	Yes	T13,T6,T9	OUTPUT

*Tests covering at least one bit in the range