Unified Coverage Report :: Module :: tlul_rsp_intg_chk

Module : tlul_rsp_intg_chk

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk	94.44	100.00	83.33				100.00

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44	100.00	83.33				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.87	100.00	83.33	72.14			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
86.96	92.86	75.00			80.00	100.00	tl_adapter_host_sba

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rsp_data_intg_check.u_tlul_data_integ_dec	100.00	100.00		100.00
u_chk	55.00			55.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : tlul_rsp_intg_chk

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	23	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	50	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' or '../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_chk.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
23	1	1
47	1	1
50	1	1

---

Cond Coverage for Module : tlul_rsp_intg_chk

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       47
 EXPRESSION (tl_i.d_valid & (((|rsp_err)) | rsp_data_err))
             ------1-----   --------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T14
1	0	Covered	T36,T37,T38
1	1	Not Covered

 LINE       47
 SUB-EXPRESSION (((|rsp_err)) | rsp_data_err)
                 ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T69,T66
1	0	Covered	T23,T116,T66

---

Assert Coverage for Module : tlul_rsp_intg_chk

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
PayLoadWidthCheck	274	274	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	274	274	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T12	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0