Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk	55.00			55.00
tb.dut.u_reg_regs.u_chk.u_chk	89.23			89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	89.23			89.23

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.00			55.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
55.00			55.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T2,*T14,*T16	Yes	T2,T4,T17	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T2,T14,T16	Yes	T2,T4,T17	OUTPUT
syndrome_o[6:0]	Yes	Yes	T2,T17,T18	Yes	T2,T12,T14	OUTPUT
err_o[1:0]	Yes	Yes	T2,T17,T18	Yes	T2,T12,T4	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	260	143	55.00
Total Bits 0->1	130	73	56.15
Total Bits 1->0	130	70	53.85

Ports	4	2	50.00
Port Bits	260	143	55.00
Port Bits 0->1	130	73	56.15
Port Bits 1->0	130	70	53.85

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	*T14,*T16,*T7	Yes	T21,T36,T23	INPUT
data_i[56:4]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T21,T36,T23	Yes	T3,T14,T18	INPUT
data_o[3:0]	Yes	Yes	*T14,*T16,*T7	Yes	T21,T36,T23	OUTPUT
data_o[4]	No	No		No		OUTPUT
data_o[8:5]	Yes	Yes	*T61,*T62,*T63	Yes	T61,T62,T63	OUTPUT
data_o[9]	No	No		Yes	T64	OUTPUT
data_o[12:10]	Yes	Yes	*T23,*T65,*T66	Yes	T23,T65,T67	OUTPUT
data_o[13]	No	No		Yes	T18	OUTPUT
data_o[21:14]	Yes	Yes	*T68,*T69,*T39	Yes	T42,T68,T69	OUTPUT
data_o[22]	No	No		No		OUTPUT
data_o[24:23]	Yes	Yes	*T65,*T66	Yes	T65,T70,T66	OUTPUT
data_o[25]	No	No		No		OUTPUT
data_o[44:26]	Yes	Yes	*T69,*T71,*T61	Yes	T72,T69,T71	OUTPUT
data_o[45]	No	No		No		OUTPUT
data_o[50:46]	Yes	Yes	*T21,*T23,*T61	Yes	T50,T21,T23	OUTPUT
data_o[51]	No	No		Yes	T41,T73	OUTPUT
data_o[56:52]	Yes	Yes	T63,T66,T74	Yes	T63,T66,T75	OUTPUT
syndrome_o[6:0]	Yes	Yes	T21,T23,T76	Yes	T12,T14,T16	OUTPUT
err_o[1:0]	Yes	Yes	T21,T23,T76	Yes	T12,T18,T48	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T17,*T18,*T27	Yes	T2,T17,T18	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T3,T12	Yes	T1,T12,T14	INPUT
data_o[56:0]	Yes	Yes	T17,T18,T27	Yes	T2,T17,T18	OUTPUT
syndrome_o[6:0]	Yes	Yes	T17,T18,T7	Yes	T17,T18,T27	OUTPUT
err_o[1:0]	Yes	Yes	T17,T18,T27	Yes	T17,T18,T27	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T2,*T4,*T5	Yes	T2,T4,T35	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T2,T4,T5	Yes	T2,T3,T12	INPUT
data_o[56:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T35	OUTPUT
syndrome_o[6:0]	Yes	Yes	T2,T4,T6	Yes	T2,T4,T6	OUTPUT
err_o[1:0]	Yes	Yes	T2,T4,T5	Yes	T2,T4,T5	OUTPUT

*Tests covering at least one bit in the range