Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	204283	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	567376	1		T5	32		T9	16		T6	26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	487399	1		T5	16		T9	12		T17	80
values[0x0]	140858	1		T5	18		T9	24		T6	61
values[0x1]	143402	1		T5	18		T9	19		T6	50

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155954	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	615705	1		T5	37		T9	19		T6	37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3873	1		T5	1		T6	1		T17	1
valid_sources[0x01]	2845	1		T6	1		T35	7		T34	3
valid_sources[0x02]	3392	1		T14	1		T33	1		T35	89
valid_sources[0x03]	2858	1		T9	2		T33	1		T35	6
valid_sources[0x04]	2911	1		T35	32		T34	3		T32	49
valid_sources[0x05]	2977	1		T17	1		T33	1		T32	39
valid_sources[0x06]	3840	1		T17	1		T8	1		T34	6
valid_sources[0x07]	3218	1		T14	1		T35	43		T28	1
valid_sources[0x08]	3874	1		T33	2		T35	37		T34	1
valid_sources[0x09]	3057	1		T7	1		T14	1		T33	1
valid_sources[0x0a]	3647	1		T17	1		T33	3		T35	55
valid_sources[0x0b]	2655	1		T5	2		T33	3		T35	14
valid_sources[0x0c]	2949	1		T9	3		T6	2		T16	4
valid_sources[0x0d]	3333	1		T17	1		T16	2		T35	11
valid_sources[0x0e]	3672	1		T6	1		T35	36		T32	64
valid_sources[0x0f]	2792	1		T5	1		T17	1		T33	1
valid_sources[0x10]	3158	1		T5	1		T6	3		T17	1
valid_sources[0x11]	2972	1		T5	1		T6	1		T17	1
valid_sources[0x12]	2917	1		T32	36		T81	18		T82	34
valid_sources[0x13]	2633	1		T6	1		T33	1		T35	59
valid_sources[0x14]	3225	1		T12	8		T35	15		T34	1
valid_sources[0x15]	3068	1		T8	2		T18	3		T35	55
valid_sources[0x16]	3420	1		T5	1		T76	2		T35	48
valid_sources[0x17]	3289	1		T6	1		T76	4		T33	1
valid_sources[0x18]	3175	1		T12	5		T33	1		T35	24
valid_sources[0x19]	2859	1		T17	1		T35	25		T34	2
valid_sources[0x1a]	2678	1		T9	7		T6	3		T17	1
valid_sources[0x1b]	3085	1		T6	1		T7	2		T34	1
valid_sources[0x1c]	2930	1		T20	1		T33	2		T35	53
valid_sources[0x1d]	2815	1		T6	3		T8	1		T33	3
valid_sources[0x1e]	3105	1		T7	3		T18	1		T35	26
valid_sources[0x1f]	2977	1		T17	1		T14	2		T8	1
valid_sources[0x20]	2873	1		T17	1		T8	1		T13	1
valid_sources[0x21]	2617	1		T8	1		T35	81		T34	2
valid_sources[0x22]	3729	1		T18	3		T34	1		T32	45
valid_sources[0x23]	3009	1		T5	1		T8	5		T35	11
valid_sources[0x24]	2764	1		T6	1		T7	2		T18	2
valid_sources[0x25]	2976	1		T12	1		T35	36		T34	1
valid_sources[0x26]	3130	1		T6	2		T17	1		T35	40
valid_sources[0x27]	2855	1		T6	1		T18	3		T35	27
valid_sources[0x28]	2925	1		T35	12		T32	44		T81	37
valid_sources[0x29]	2953	1		T6	1		T17	1		T33	2
valid_sources[0x2a]	2592	1		T6	3		T17	1		T7	1
valid_sources[0x2b]	3043	1		T17	1		T35	8		T32	49
valid_sources[0x2c]	3344	1		T35	43		T28	1		T32	35
valid_sources[0x2d]	3433	1		T124	1		T33	1		T35	20
valid_sources[0x2e]	2898	1		T33	1		T34	2		T32	26
valid_sources[0x2f]	3564	1		T124	17		T33	1		T35	49
valid_sources[0x30]	2822	1		T17	1		T8	3		T33	1
valid_sources[0x31]	3949	1		T17	1		T35	11		T34	1
valid_sources[0x32]	2847	1		T14	1		T35	20		T34	4
valid_sources[0x33]	3047	1		T35	3		T34	4		T32	33
valid_sources[0x34]	3042	1		T76	6		T35	28		T34	2
valid_sources[0x35]	2815	1		T5	1		T6	3		T35	60
valid_sources[0x36]	2930	1		T33	2		T35	22		T34	5
valid_sources[0x37]	2666	1		T6	2		T33	1		T35	50
valid_sources[0x38]	2832	1		T5	1		T20	1		T33	2
valid_sources[0x39]	2584	1		T5	1		T17	1		T8	2
valid_sources[0x3a]	2859	1		T34	1		T32	30		T81	4
valid_sources[0x3b]	3125	1		T6	1		T33	1		T35	34
valid_sources[0x3c]	2957	1		T5	2		T35	26		T28	1
valid_sources[0x3d]	2946	1		T7	4		T34	2		T32	44
valid_sources[0x3e]	3327	1		T33	2		T35	96		T34	2
valid_sources[0x3f]	2768	1		T9	1		T6	1		T8	1
valid_sources[0x40]	2830	1		T17	3		T8	2		T33	1
valid_sources[0x41]	3066	1		T6	1		T7	3		T33	1
valid_sources[0x42]	3128	1		T8	1		T33	3		T35	20
valid_sources[0x43]	2991	1		T35	28		T32	38		T81	22
valid_sources[0x44]	2667	1		T33	2		T35	51		T34	1
valid_sources[0x45]	2752	1		T6	1		T8	1		T32	53
valid_sources[0x46]	2936	1		T33	2		T35	4		T34	3
valid_sources[0x47]	2883	1		T7	1		T8	2		T33	1
valid_sources[0x48]	3291	1		T17	1		T8	2		T35	65
valid_sources[0x49]	3070	1		T5	1		T6	1		T35	25
valid_sources[0x4a]	2543	1		T6	1		T35	43		T34	1
valid_sources[0x4b]	3327	1		T14	2		T8	1		T35	7
valid_sources[0x4c]	2419	1		T5	2		T18	3		T33	1
valid_sources[0x4d]	3049	1		T14	1		T33	1		T35	23
valid_sources[0x4e]	3214	1		T9	1		T33	1		T34	1
valid_sources[0x4f]	2870	1		T20	1		T8	1		T18	4
valid_sources[0x50]	2703	1		T8	1		T33	2		T35	9
valid_sources[0x51]	3156	1		T6	1		T7	1		T33	2
valid_sources[0x52]	2598	1		T14	1		T8	1		T35	21
valid_sources[0x53]	2527	1		T8	1		T12	3		T34	2
valid_sources[0x54]	2878	1		T5	2		T8	2		T33	1
valid_sources[0x55]	4077	1		T14	3		T35	21		T34	2
valid_sources[0x56]	2906	1		T7	2		T35	32		T34	1
valid_sources[0x57]	2939	1		T9	3		T16	4		T14	1
valid_sources[0x58]	2653	1		T8	1		T76	13		T124	1
valid_sources[0x59]	3154	1		T8	1		T33	2		T35	13
valid_sources[0x5a]	2515	1		T7	1		T14	1		T34	1
valid_sources[0x5b]	2764	1		T5	1		T9	3		T6	1
valid_sources[0x5c]	3465	1		T17	3		T8	2		T33	2
valid_sources[0x5d]	3298	1		T6	1		T33	1		T35	7
valid_sources[0x5e]	3161	1		T6	1		T12	3		T35	17
valid_sources[0x5f]	2519	1		T17	1		T14	1		T35	36
valid_sources[0x60]	3067	1		T9	7		T33	2		T35	38
valid_sources[0x61]	3147	1		T6	2		T8	1		T33	1
valid_sources[0x62]	2968	1		T6	1		T8	1		T35	12
valid_sources[0x63]	2567	1		T5	1		T6	1		T16	1
valid_sources[0x64]	2878	1		T33	1		T35	35		T34	1
valid_sources[0x65]	2575	1		T17	1		T8	1		T35	38
valid_sources[0x66]	2485	1		T5	1		T18	6		T33	1
valid_sources[0x67]	3481	1		T5	1		T35	39		T32	62
valid_sources[0x68]	3106	1		T17	1		T35	8		T34	11
valid_sources[0x69]	2551	1		T5	1		T14	1		T33	1
valid_sources[0x6a]	3685	1		T17	1		T33	3		T35	30
valid_sources[0x6b]	3169	1		T6	2		T17	1		T32	43
valid_sources[0x6c]	2721	1		T5	1		T8	1		T18	10
valid_sources[0x6d]	2264	1		T33	2		T35	8		T34	1
valid_sources[0x6e]	2850	1		T14	1		T33	2		T35	17
valid_sources[0x6f]	3169	1		T5	3		T6	2		T76	2
valid_sources[0x70]	3076	1		T33	2		T35	1		T34	4
valid_sources[0x71]	2587	1		T14	1		T8	2		T33	4
valid_sources[0x72]	2768	1		T6	3		T7	1		T8	2
valid_sources[0x73]	3226	1		T6	1		T33	2		T35	10
valid_sources[0x74]	3245	1		T8	1		T35	7		T34	1
valid_sources[0x75]	3157	1		T5	1		T17	1		T7	2
valid_sources[0x76]	2732	1		T17	1		T20	1		T8	4
valid_sources[0x77]	2727	1		T9	3		T17	2		T8	1
valid_sources[0x78]	2740	1		T8	1		T34	1		T32	39
valid_sources[0x79]	2973	1		T6	1		T33	1		T35	16
valid_sources[0x7a]	2695	1		T7	3		T33	2		T35	47
valid_sources[0x7b]	3115	1		T17	1		T33	5		T35	21
valid_sources[0x7c]	2732	1		T5	1		T14	1		T35	25
valid_sources[0x7d]	2887	1		T6	1		T17	1		T14	1
valid_sources[0x7e]	2892	1		T6	1		T33	1		T35	38
valid_sources[0x7f]	2889	1		T17	1		T33	1		T35	38
valid_sources[0x80]	2663	1		T8	2		T32	43		T81	54

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

290824

1

T5

10

T9

7

T17

80

values[0x0]

all_enables

biggest_size

139066

1

T5

10

T9

6

T6

17

values[0x1]

all_enables

biggest_size

137486

1

T5

12

T9

3

T6

9

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	4994	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	20439	1		T1	8		T2	2		T3	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	9993	1		T33	23		T35	34		T34	28
values[0x0]	7602	1		T1	7		T2	9		T3	2
values[0x1]	7838	1		T1	8		T2	8		T3	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3836	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	21597	1		T1	8		T2	2		T3	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	74	1		T2	1		T28	2		T32	1
valid_sources[0x01]	89	1		T28	3		T82	2		T71	2
valid_sources[0x02]	75	1		T125	1		T126	1		T28	2
valid_sources[0x03]	59	1		T34	1		T28	5		T78	1
valid_sources[0x04]	65	1		T34	1		T28	3		T32	1
valid_sources[0x05]	62	1		T28	6		T77	1		T71	6
valid_sources[0x06]	81	1		T127	1		T33	2		T34	1
valid_sources[0x07]	76	1		T128	1		T35	1		T28	4
valid_sources[0x08]	71	1		T28	5		T71	3		T87	1
valid_sources[0x09]	61	1		T21	3		T28	8		T32	2
valid_sources[0x0a]	69	1		T60	1		T28	8		T32	7
valid_sources[0x0b]	152	1		T28	2		T32	3		T29	55
valid_sources[0x0c]	114	1		T129	1		T34	1		T28	4
valid_sources[0x0d]	168	1		T28	8		T71	2		T80	1
valid_sources[0x0e]	80	1		T34	1		T28	5		T32	1
valid_sources[0x0f]	55	1		T28	7		T78	1		T71	1
valid_sources[0x10]	219	1		T128	2		T28	7		T29	146
valid_sources[0x11]	90	1		T54	2		T28	4		T130	2
valid_sources[0x12]	50	1		T28	9		T71	1		T80	1
valid_sources[0x13]	82	1		T131	1		T34	2		T28	4
valid_sources[0x14]	166	1		T28	4		T81	24		T130	1
valid_sources[0x15]	82	1		T40	1		T132	17		T34	1
valid_sources[0x16]	68	1		T133	1		T28	7		T82	1
valid_sources[0x17]	90	1		T35	2		T34	1		T28	5
valid_sources[0x18]	78	1		T28	5		T82	1		T30	20
valid_sources[0x19]	156	1		T72	1		T131	1		T28	2
valid_sources[0x1a]	84	1		T60	1		T28	4		T32	4
valid_sources[0x1b]	59	1		T28	7		T78	1		T71	4
valid_sources[0x1c]	81	1		T34	1		T28	4		T82	1
valid_sources[0x1d]	51	1		T28	4		T82	1		T77	1
valid_sources[0x1e]	109	1		T38	1		T28	4		T78	1
valid_sources[0x1f]	91	1		T125	1		T34	2		T28	4
valid_sources[0x20]	58	1		T28	5		T32	1		T78	1
valid_sources[0x21]	217	1		T34	1		T28	7		T32	2
valid_sources[0x22]	70	1		T4	1		T34	1		T28	4
valid_sources[0x23]	53	1		T28	2		T130	2		T134	1
valid_sources[0x24]	75	1		T135	1		T28	5		T32	1
valid_sources[0x25]	98	1		T28	3		T32	1		T69	3
valid_sources[0x26]	104	1		T22	6		T33	2		T28	5
valid_sources[0x27]	85	1		T136	1		T35	5		T28	10
valid_sources[0x28]	75	1		T28	10		T71	5		T130	1
valid_sources[0x29]	66	1		T34	1		T28	4		T32	2
valid_sources[0x2a]	61	1		T34	1		T28	3		T130	2
valid_sources[0x2b]	135	1		T28	2		T29	54		T78	1
valid_sources[0x2c]	52	1		T28	1		T32	3		T82	1
valid_sources[0x2d]	112	1		T34	2		T28	5		T32	1
valid_sources[0x2e]	76	1		T38	1		T28	3		T79	1
valid_sources[0x2f]	62	1		T4	2		T28	3		T32	2
valid_sources[0x30]	58	1		T4	1		T34	1		T28	3
valid_sources[0x31]	64	1		T34	1		T28	3		T77	1
valid_sources[0x32]	87	1		T22	3		T38	3		T28	4
valid_sources[0x33]	89	1		T33	8		T28	2		T69	1
valid_sources[0x34]	66	1		T34	2		T28	5		T77	1
valid_sources[0x35]	132	1		T60	1		T35	4		T28	2
valid_sources[0x36]	71	1		T34	1		T77	1		T79	1
valid_sources[0x37]	115	1		T28	2		T78	2		T71	7
valid_sources[0x38]	311	1		T28	3		T69	2		T78	1
valid_sources[0x39]	99	1		T137	1		T138	4		T34	1
valid_sources[0x3a]	59	1		T33	2		T28	6		T78	2
valid_sources[0x3b]	91	1		T4	1		T28	4		T82	1
valid_sources[0x3c]	59	1		T28	3		T82	1		T71	1
valid_sources[0x3d]	66	1		T28	4		T71	2		T130	2
valid_sources[0x3e]	116	1		T34	1		T28	8		T29	43
valid_sources[0x3f]	76	1		T28	2		T32	1		T82	2
valid_sources[0x40]	84	1		T33	3		T28	5		T30	1
valid_sources[0x41]	278	1		T28	4		T82	2		T29	4
valid_sources[0x42]	69	1		T133	1		T28	4		T32	1
valid_sources[0x43]	57	1		T33	3		T28	4		T78	2
valid_sources[0x44]	122	1		T28	5		T71	2		T89	7
valid_sources[0x45]	88	1		T33	1		T28	5		T82	1
valid_sources[0x46]	87	1		T25	12		T53	2		T55	6
valid_sources[0x47]	72	1		T34	1		T28	3		T78	1
valid_sources[0x48]	97	1		T28	4		T77	1		T71	6
valid_sources[0x49]	76	1		T33	10		T34	1		T28	3
valid_sources[0x4a]	58	1		T28	1		T81	6		T78	1
valid_sources[0x4b]	85	1		T60	1		T35	8		T34	2
valid_sources[0x4c]	77	1		T28	2		T32	1		T29	33
valid_sources[0x4d]	75	1		T60	1		T19	1		T40	1
valid_sources[0x4e]	65	1		T136	1		T133	1		T78	1
valid_sources[0x4f]	110	1		T23	4		T28	4		T78	1
valid_sources[0x50]	267	1		T3	1		T35	7		T34	2
valid_sources[0x51]	66	1		T28	5		T32	1		T82	1
valid_sources[0x52]	77	1		T139	1		T33	1		T34	1
valid_sources[0x53]	92	1		T34	1		T28	2		T78	1
valid_sources[0x54]	79	1		T140	12		T28	3		T77	1
valid_sources[0x55]	62	1		T34	1		T28	6		T79	3
valid_sources[0x56]	86	1		T141	1		T35	10		T34	1
valid_sources[0x57]	107	1		T28	3		T29	45		T71	1
valid_sources[0x58]	225	1		T4	1		T107	2		T28	5
valid_sources[0x59]	90	1		T34	1		T28	5		T32	3
valid_sources[0x5a]	86	1		T28	5		T82	1		T29	2
valid_sources[0x5b]	73	1		T50	6		T61	7		T28	6
valid_sources[0x5c]	73	1		T34	1		T28	7		T77	1
valid_sources[0x5d]	110	1		T126	1		T28	2		T78	1
valid_sources[0x5e]	94	1		T35	4		T34	1		T28	4
valid_sources[0x5f]	69	1		T34	1		T28	4		T71	8
valid_sources[0x60]	211	1		T3	6		T33	1		T34	2
valid_sources[0x61]	71	1		T2	2		T22	1		T28	6
valid_sources[0x62]	93	1		T133	1		T33	1		T28	4
valid_sources[0x63]	72	1		T34	1		T28	4		T71	2
valid_sources[0x64]	58	1		T28	3		T32	1		T71	1
valid_sources[0x65]	147	1		T28	4		T32	1		T78	3
valid_sources[0x66]	118	1		T28	5		T82	2		T29	32
valid_sources[0x67]	85	1		T135	7		T28	6		T82	1
valid_sources[0x68]	59	1		T57	1		T35	1		T28	4
valid_sources[0x69]	66	1		T2	3		T34	2		T28	5
valid_sources[0x6a]	67	1		T28	6		T71	5		T130	3
valid_sources[0x6b]	68	1		T2	1		T131	3		T28	3
valid_sources[0x6c]	123	1		T28	10		T32	1		T29	2
valid_sources[0x6d]	133	1		T72	1		T34	1		T28	1
valid_sources[0x6e]	62	1		T28	4		T32	2		T78	1
valid_sources[0x6f]	74	1		T34	1		T28	2		T32	4
valid_sources[0x70]	111	1		T136	1		T142	1		T28	4
valid_sources[0x71]	68	1		T33	1		T28	3		T78	1
valid_sources[0x72]	50	1		T34	1		T28	2		T79	2
valid_sources[0x73]	88	1		T136	1		T28	3		T32	6
valid_sources[0x74]	68	1		T54	1		T28	4		T84	2
valid_sources[0x75]	123	1		T28	1		T32	1		T82	1
valid_sources[0x76]	79	1		T136	1		T28	3		T78	1
valid_sources[0x77]	258	1		T28	5		T71	2		T130	3
valid_sources[0x78]	111	1		T28	6		T29	22		T78	1
valid_sources[0x79]	93	1		T141	2		T28	8		T32	3
valid_sources[0x7a]	72	1		T139	1		T35	4		T34	1
valid_sources[0x7b]	105	1		T28	8		T78	1		T111	2
valid_sources[0x7c]	103	1		T28	3		T82	1		T78	1
valid_sources[0x7d]	85	1		T143	1		T141	1		T33	1
valid_sources[0x7e]	91	1		T142	11		T28	3		T71	1
valid_sources[0x7f]	219	1		T4	3		T52	1		T28	2
valid_sources[0x80]	71	1		T22	4		T34	2		T28	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

6956

1

T33

19

T35

34

T34

17

values[0x0]

all_enables

biggest_size

6889

1

T1

4

T2

1

T3

2

values[0x1]

all_enables

biggest_size

6594

1

T1

4

T2

1

T3

2