Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 240403 1 T5 20 T9 39 T6 85
full_word 569086 1 T5 32 T9 16 T6 26



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 809189 1 T5 52 T9 55 T6 111
auto[TlIntgErrCmd] 107 1 T32 6 T80 2 T111 4
auto[TlIntgErrData] 86 1 T32 6 T80 5 T111 2
auto[TlIntgErrBoth] 107 1 T32 8 T80 3 T111 4



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 489468 1 T5 16 T9 12 T17 80
auto[1] 320021 1 T5 36 T9 43 T6 111



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 198314 1 T5 6 T9 5 T7 14
auto[TlIntgErrNone] partial auto[1] 41818 1 T5 14 T9 34 T6 85
auto[TlIntgErrNone] full_word auto[0] 291027 1 T5 10 T9 7 T17 80
auto[TlIntgErrNone] full_word auto[1] 278030 1 T5 22 T9 9 T6 26
auto[TlIntgErrCmd] partial auto[0] 42 1 T32 2 T111 2 T115 5
auto[TlIntgErrCmd] partial auto[1] 56 1 T32 3 T80 2 T111 1
auto[TlIntgErrCmd] full_word auto[0] 2 1 T111 1 T119 1 - -
auto[TlIntgErrCmd] full_word auto[1] 7 1 T32 1 T116 1 T70 1
auto[TlIntgErrData] partial auto[0] 38 1 T32 5 T80 2 T111 1
auto[TlIntgErrData] partial auto[1] 39 1 T32 1 T80 3 T111 1
auto[TlIntgErrData] full_word auto[0] 5 1 T70 1 T121 1 T63 1
auto[TlIntgErrData] full_word auto[1] 4 1 T115 1 T116 1 T122 1
auto[TlIntgErrBoth] partial auto[0] 36 1 T32 4 T80 1 T111 2
auto[TlIntgErrBoth] partial auto[1] 60 1 T32 4 T111 2 T113 3
auto[TlIntgErrBoth] full_word auto[0] 4 1 T115 1 T123 1 T122 1
auto[TlIntgErrBoth] full_word auto[1] 7 1 T80 2 T120 1 T123 1

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