Module Definition
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Module : rv_dm_regs_csr_assert_fpv
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.rv_dm_regs_csr_assert 100.00 100.00



Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
85.64 100.00 55.32 85.38 100.00 87.50 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : rv_dm_regs_csr_assert_fpv
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
TlulOOBAddrErr_A 31011516 14278 0 0
late_debug_enable_rd_A 31011516 3845 0 0
late_debug_enable_regwen_rd_A 31011516 4828 0 0


TlulOOBAddrErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31011516 14278 0 0
T28 149743 312 0 0
T29 119026 1305 0 0
T30 333846 25 0 0
T32 49864 4 0 0
T33 4157 238 0 0
T34 5077 635 0 0
T71 344750 174 0 0
T77 3925 14 0 0
T78 7004 361 0 0
T79 61914 19 0 0

late_debug_enable_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31011516 3845 0 0
T79 61914 25 0 0
T80 42767 49 0 0
T81 53764 59 0 0
T83 10001 10 0 0
T86 54468 43 0 0
T89 428364 5 0 0
T91 10885 1 0 0
T108 7524 23 0 0
T109 8467 28 0 0
T110 746606 67 0 0

late_debug_enable_regwen_rd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31011516 4828 0 0
T79 61914 20 0 0
T80 42767 41 0 0
T81 53764 63 0 0
T83 10001 6 0 0
T86 54468 55 0 0
T89 428364 49 0 0
T90 5435 6 0 0
T91 10885 16 0 0
T108 7524 14 0 0
T109 8467 9 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%