Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T12 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T12 |
1 | 1 | Covered | T9,T12 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T12 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
10598518 |
10597810 |
0 |
0 |
selKnown1 |
12530499 |
12529791 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
10598518 |
10597810 |
0 |
0 |
T1 |
306 |
304 |
0 |
0 |
T2 |
426 |
424 |
0 |
0 |
T3 |
392 |
390 |
0 |
0 |
T4 |
306 |
304 |
0 |
0 |
T5 |
95920 |
95916 |
0 |
0 |
T6 |
0 |
12 |
0 |
0 |
T7 |
0 |
14 |
0 |
0 |
T9 |
0 |
11 |
0 |
0 |
T14 |
0 |
27 |
0 |
0 |
T16 |
0 |
32 |
0 |
0 |
T19 |
2 |
0 |
0 |
0 |
T21 |
356 |
354 |
0 |
0 |
T22 |
342 |
338 |
0 |
0 |
T23 |
392 |
388 |
0 |
0 |
T24 |
7450 |
7446 |
0 |
0 |
T25 |
352 |
348 |
0 |
0 |
T26 |
0 |
40 |
0 |
0 |
T27 |
0 |
20 |
0 |
0 |
T38 |
2 |
0 |
0 |
0 |
T50 |
2 |
0 |
0 |
0 |
T54 |
2 |
0 |
0 |
0 |
T58 |
0 |
40 |
0 |
0 |
T60 |
2 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
12530499 |
12529791 |
0 |
0 |
T1 |
1450 |
1448 |
0 |
0 |
T2 |
1356 |
1354 |
0 |
0 |
T3 |
1147 |
1145 |
0 |
0 |
T4 |
2746 |
2744 |
0 |
0 |
T5 |
204315 |
204311 |
0 |
0 |
T6 |
0 |
2 |
0 |
0 |
T7 |
0 |
8 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T14 |
0 |
8 |
0 |
0 |
T16 |
0 |
6 |
0 |
0 |
T19 |
2 |
0 |
0 |
0 |
T21 |
2508 |
2506 |
0 |
0 |
T22 |
1646 |
1642 |
0 |
0 |
T23 |
2352 |
2348 |
0 |
0 |
T24 |
12498 |
12494 |
0 |
0 |
T25 |
1519 |
1515 |
0 |
0 |
T26 |
0 |
40 |
0 |
0 |
T27 |
0 |
20 |
0 |
0 |
T38 |
2 |
0 |
0 |
0 |
T50 |
2 |
0 |
0 |
0 |
T54 |
2 |
0 |
0 |
0 |
T58 |
0 |
40 |
0 |
0 |
T60 |
2 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 8 | 88.89 |
Logical | 9 | 8 | 88.89 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T12 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T12 |
1 | 1 | Covered | T9,T12 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
706878 |
706805 |
0 |
0 |
selKnown1 |
2639084 |
2639011 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
706878 |
706805 |
0 |
0 |
T1 |
153 |
152 |
0 |
0 |
T2 |
213 |
212 |
0 |
0 |
T3 |
196 |
195 |
0 |
0 |
T4 |
153 |
152 |
0 |
0 |
T5 |
47954 |
47953 |
0 |
0 |
T21 |
178 |
177 |
0 |
0 |
T22 |
170 |
169 |
0 |
0 |
T23 |
195 |
194 |
0 |
0 |
T24 |
3704 |
3703 |
0 |
0 |
T25 |
175 |
174 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2639084 |
2639011 |
0 |
0 |
T1 |
1297 |
1296 |
0 |
0 |
T2 |
1143 |
1142 |
0 |
0 |
T3 |
951 |
950 |
0 |
0 |
T4 |
2593 |
2592 |
0 |
0 |
T5 |
156349 |
156348 |
0 |
0 |
T21 |
2330 |
2329 |
0 |
0 |
T22 |
1474 |
1473 |
0 |
0 |
T23 |
2155 |
2154 |
0 |
0 |
T24 |
8752 |
8751 |
0 |
0 |
T25 |
1342 |
1341 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 8 | 88.89 |
Logical | 9 | 8 | 88.89 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T12 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T12 |
1 | 1 | Covered | T9,T12 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
236 |
163 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T7 |
0 |
4 |
0 |
0 |
T9 |
0 |
3 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T16 |
0 |
16 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
21 |
20 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
20 |
0 |
0 |
T27 |
0 |
10 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T54 |
1 |
0 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
201 |
128 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
0 |
1 |
0 |
0 |
T7 |
0 |
4 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T16 |
0 |
3 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
21 |
20 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
20 |
0 |
0 |
T27 |
0 |
10 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T54 |
1 |
0 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T12 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T12 |
1 | 1 | Covered | T9,T12 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T12 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9889702 |
9889421 |
0 |
0 |
selKnown1 |
9889702 |
9889421 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9889702 |
9889421 |
0 |
0 |
T1 |
153 |
152 |
0 |
0 |
T2 |
213 |
212 |
0 |
0 |
T3 |
196 |
195 |
0 |
0 |
T4 |
153 |
152 |
0 |
0 |
T5 |
47954 |
47953 |
0 |
0 |
T21 |
178 |
177 |
0 |
0 |
T22 |
170 |
169 |
0 |
0 |
T23 |
195 |
194 |
0 |
0 |
T24 |
3704 |
3703 |
0 |
0 |
T25 |
175 |
174 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9889702 |
9889421 |
0 |
0 |
T1 |
153 |
152 |
0 |
0 |
T2 |
213 |
212 |
0 |
0 |
T3 |
196 |
195 |
0 |
0 |
T4 |
153 |
152 |
0 |
0 |
T5 |
47954 |
47953 |
0 |
0 |
T21 |
178 |
177 |
0 |
0 |
T22 |
170 |
169 |
0 |
0 |
T23 |
195 |
194 |
0 |
0 |
T24 |
3704 |
3703 |
0 |
0 |
T25 |
175 |
174 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T12 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T9,T12 |
1 | 1 | Covered | T9,T12 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T9,T12 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1702 |
1421 |
0 |
0 |
selKnown1 |
1512 |
1231 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1702 |
1421 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
0 |
6 |
0 |
0 |
T7 |
0 |
10 |
0 |
0 |
T9 |
0 |
8 |
0 |
0 |
T14 |
0 |
23 |
0 |
0 |
T16 |
0 |
16 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
21 |
20 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
20 |
0 |
0 |
T27 |
0 |
10 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T54 |
1 |
0 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1512 |
1231 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
0 |
1 |
0 |
0 |
T7 |
0 |
4 |
0 |
0 |
T9 |
0 |
4 |
0 |
0 |
T14 |
0 |
4 |
0 |
0 |
T16 |
0 |
3 |
0 |
0 |
T19 |
1 |
0 |
0 |
0 |
T22 |
1 |
0 |
0 |
0 |
T23 |
1 |
0 |
0 |
0 |
T24 |
21 |
20 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T26 |
0 |
20 |
0 |
0 |
T27 |
0 |
10 |
0 |
0 |
T38 |
1 |
0 |
0 |
0 |
T50 |
1 |
0 |
0 |
0 |
T54 |
1 |
0 |
0 |
0 |
T58 |
0 |
20 |
0 |
0 |
T60 |
1 |
0 |
0 |
0 |