Unified Coverage Report :: Module :: prim_mubi32_sync

Module : prim_mubi32_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi32_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_mubi32_sync_late_debug_enable	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_mubi32_sync_late_debug_enable

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.64	100.00	55.32	85.38		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[10].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[11].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[12].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[13].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[14].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[15].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[16].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[17].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[18].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[19].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[20].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[21].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[22].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[23].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[24].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[25].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[26].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[27].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[28].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[29].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[30].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[31].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[7].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[8].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[9].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[10].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[11].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[12].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[13].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[14].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[15].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[16].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[17].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[18].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[19].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[20].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[21].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[22].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[23].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[24].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[25].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[26].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[27].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[28].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[29].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[30].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[31].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[7].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[8].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[9].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[10].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[11].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[12].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[13].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[14].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[15].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[16].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[17].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[18].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[19].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[20].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[21].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[22].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[23].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[24].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[25].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[26].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[27].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[28].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[29].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[30].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[31].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[7].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[8].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[9].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[10].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[11].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[12].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[13].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[14].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[15].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[16].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[17].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[18].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[19].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[20].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[21].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[22].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[23].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[24].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[25].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[26].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[27].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[28].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[29].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[30].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[31].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[4].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[5].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[6].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[7].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[8].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[9].u_prim_buf	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_mubi32_sync

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
ALWAYS	145	0	0
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00
CONT_ASSIGN	168	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi32_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi32_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
145		unreachable
146		unreachable
148		unreachable
155	1	1
168	4	4

---

Assert Coverage for Module : prim_mubi32_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	73	73	0	0
OutputsKnown_A	2639084	2625573	0	0
gen_no_flops.OutputDelay_A	2639084	2625573	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	73	73	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T21	1	1	0	0
T22	1	1	0	0
T23	1	1	0	0
T24	1	1	0	0
T25	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2639084	2625573	0	0
T1	1297	1240	0	0
T2	1143	1078	0	0
T3	951	900	0	0
T4	2593	2519	0	0
T5	156349	155946	0	0
T21	2330	2260	0	0
T22	1474	1404	0	0
T23	2155	2074	0	0
T24	8752	7339	0	0
T25	1342	1289	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2639084	2625573	0	0
T1	1297	1240	0	0
T2	1143	1078	0	0
T3	951	900	0	0
T4	2593	2519	0	0
T5	156349	155946	0	0
T21	2330	2260	0	0
T22	1474	1404	0	0
T23	2155	2074	0	0
T24	8752	7339	0	0
T25	1342	1289	0	0