Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk	57.69			57.69
tb.dut.u_reg_regs.u_chk.u_chk	89.23			89.23
tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk	89.23			89.23

---

Module Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
57.69			57.69

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
57.69			57.69

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44	100.00	83.33				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_regs.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23			89.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_cmd_intg_check.u_cmd_intg_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T5,*T22,*T24	Yes	T3,T5,T22	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T5,T22,T24	Yes	T3,T5,T22	OUTPUT
syndrome_o[6:0]	Yes	Yes	T5,T22,T24	Yes	T2,T3,T5	OUTPUT
err_o[1:0]	Yes	Yes	T5,T22,T24	Yes	T5,T22,T24	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	4	2	50.00
Total Bits	260	150	57.69
Total Bits 0->1	130	77	59.23
Total Bits 1->0	130	73	56.15

Ports	4	2	50.00
Port Bits	260	150	57.69
Port Bits 0->1	130	77	59.23
Port Bits 1->0	130	73	56.15

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[3:0]	Yes	Yes	T24,*T50,*T36	Yes	T24,T8,T12	INPUT
data_i[56:4]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T24,T8,T12	Yes	T2,T24,T54	INPUT
data_o[4:0]	Yes	Yes	*T24,*T50,*T36	Yes	T24,T8,T12	OUTPUT
data_o[5]	No	No		Yes	T54,T63	OUTPUT
data_o[9:6]	Yes	Yes	*T24,*T30,*T64	Yes	T24,T30,T64	OUTPUT
data_o[10]	No	No		Yes	T65	OUTPUT
data_o[17:11]	Yes	Yes	*T8,*T66,*T67	Yes	T8,T66,T67	OUTPUT
data_o[18]	No	No		Yes	T68	OUTPUT
data_o[29:19]	Yes	Yes	*T69,*T30,*T70	Yes	T11,T69,T30	OUTPUT
data_o[30]	No	No		Yes	T42	OUTPUT
data_o[56:31]	Yes	Yes	T66,T71,T65	Yes	T66,T71,T65	OUTPUT
syndrome_o[6:0]	Yes	Yes	T24,T8,T12	Yes	T24,T54,T36	OUTPUT
err_o[1:0]	Yes	Yes	T24,T8,T12	Yes	T24,T54,T19	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T22,*T24,*T19	Yes	T22,T24,T19	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T22,T24,T19	Yes	T22,T24,T19	OUTPUT
syndrome_o[6:0]	Yes	Yes	T22,T24,T19	Yes	T22,T24,T19	OUTPUT
err_o[1:0]	Yes	Yes	T22,T24,T19	Yes	T22,T24,T19	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	260	232	89.23
Total Bits 0->1	130	116	89.23
Total Bits 1->0	130	116	89.23

Ports	4	3	75.00
Port Bits	260	232	89.23
Port Bits 0->1	130	116	89.23
Port Bits 1->0	130	116	89.23

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T5,*T9,*T6	Yes	T3,T5,T38	INPUT
data_i[56:43]	No	No		No		INPUT
data_i[63:57]	Yes	Yes	T5,T9,T6	Yes	T3,T4,T5	INPUT
data_o[56:0]	Yes	Yes	T5,T9,T6	Yes	T3,T5,T38	OUTPUT
syndrome_o[6:0]	Yes	Yes	T5,T9,T26	Yes	T2,T3,T5	OUTPUT
err_o[1:0]	Yes	Yes	T5,T19,T15	Yes	T5,T9,T6	OUTPUT

*Tests covering at least one bit in the range