RV_DM Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 0.690s 7.039us 0 2 0.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.950s 99.897us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.970s 166.280us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 3.620s 1.665ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 0.920s 57.508us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 5.990s 1.749ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 4.200s 1.167ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 4.459m 84.296ms 5 5 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 31.110s 8.262ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 0.710s 47.844us 0 2 0.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.670s 32.246us 0 2 0.00
V1 cmderr_exception rv_dm_cmderr_exception 0.720s 46.607us 0 2 0.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 0.690s 9.377us 0 2 0.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.700s 36.532us 0 2 0.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 0.710s 14.113us 0 2 0.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.670s 34.050us 0 2 0.00
V1 halt_resume rv_dm_halt_resume_whereto 0.780s 62.062us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 0.700s 9.981us 0 2 0.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.710s 26.288us 0 2 0.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.770s 53.893us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 0.720s 46.607us 0 2 0.00
V1 rom_read_access rv_dm_rom_read_access 0.850s 31.717us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.330s 72.941us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.940s 1.322ms 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 54.690s 5.397ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.319m 8.425ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 12.210s 4.614ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.319m 8.425ms 5 5 100.00
rv_dm_csr_rw 2.940s 1.322ms 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.730s 24.071us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.730s 21.435us 5 5 100.00
V1 TOTAL 139 161 86.34
V2 idcode rv_dm_smoke 0.690s 7.039us 0 2 0.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 0.690s 47.159us 0 2 0.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.820s 68.438us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0.780s 196.029us 0 2 0.00
V2 sba rv_dm_sba_tl_access 0.800s 47.072us 0 20 0.00
rv_dm_delayed_resp_sba_tl_access 0.840s 65.436us 0 20 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 0.850s 103.442us 0 20 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 0.790s 54.649us 0 20 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.680s 14.899us 0 2 0.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 0.770s 91.022us 0 2 0.00
V2 hart_unavail rv_dm_hart_unavail 0.670s 16.085us 0 5 0.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 0.640s 5.830us 0 1 0.00
rv_dm_tap_fsm_rand_reset 51.730s 17.314ms 12 40 30.00
V2 stress_all rv_dm_stress_all 17.910s 5.206ms 9 50 18.00
V2 alert_test rv_dm_alert_test 0.800s 21.626us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.420s 108.664us 18 20 90.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.420s 108.664us 18 20 90.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.319m 8.425ms 5 5 100.00
rv_dm_csr_hw_reset 2.330s 72.941us 5 5 100.00
rv_dm_csr_rw 2.940s 1.322ms 20 20 100.00
rv_dm_same_csr_outstanding 8.240s 1.716ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.319m 8.425ms 5 5 100.00
rv_dm_csr_hw_reset 2.330s 72.941us 5 5 100.00
rv_dm_csr_rw 2.940s 1.322ms 20 20 100.00
rv_dm_same_csr_outstanding 8.240s 1.716ms 20 20 100.00
V2 TOTAL 111 276 40.22
V2S tl_intg_err rv_dm_sec_cm 1.870s 291.968us 5 5 100.00
rv_dm_tl_intg_err 21.120s 5.179ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 2.299m 87.772ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 275 512 53.71

Testplan Progress

Items Total Written Passing Progress
V1 28 28 17 60.71
V2 18 16 3 16.67
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
75.05 90.63 76.24 86.17 60.26 77.17 98.42 36.48

Failure Buckets

Past Results