69c572b503| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 2.130s | 445.491us | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 1.070s | 117.611us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.900s | 89.674us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 13.910s | 4.427ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0.820s | 94.261us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 2.690s | 2.458ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 3.300s | 836.764us | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 1.448m | 50.000ms | 4 | 5 | 80.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 57.170s | 16.545ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 6.180s | 2.343ms | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 4.630s | 6.682ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.590s | 310.630us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 3.150s | 969.942us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.220s | 173.268us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 1.580s | 280.977us | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.780s | 112.069us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 0.750s | 32.973us | 0 | 2 | 0.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 1.490s | 236.903us | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.910s | 76.771us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 0.850s | 141.598us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.590s | 310.630us | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.820s | 74.667us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.280s | 167.243us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.570s | 1.148ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.188m | 8.134ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.282m | 9.148ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 9.510s | 3.823ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.282m | 9.148ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.570s | 1.148ms | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.720s | 61.550us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.780s | 27.218us | 5 | 5 | 100.00 |
| V1 | TOTAL | 158 | 161 | 98.14 | |||
| V2 | idcode | rv_dm_smoke | 2.130s | 445.491us | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 2.750s | 1.171ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 2.302m | 50.000ms | 0 | 2 | 0.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.010s | 110.389us | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 7.370s | 2.747ms | 1 | 20 | 5.00 |
| rv_dm_delayed_resp_sba_tl_access | 6.240s | 3.217ms | 4 | 20 | 20.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 3.860s | 1.080ms | 1 | 20 | 5.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 20.660s | 50.000ms | 0 | 20 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.800s | 62.815us | 1 | 2 | 50.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 1.450s | 1.710ms | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.900s | 82.583us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 4.500s | 3.908ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 44.940s | 12.487ms | 11 | 40 | 27.50 | ||
| V2 | stress_all | rv_dm_stress_all | 2.993h | 10.000s | 1 | 50 | 2.00 |
| V2 | alert_test | rv_dm_alert_test | 0.840s | 33.133us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.850s | 695.818us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.850s | 695.818us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.282m | 9.148ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.280s | 167.243us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.570s | 1.148ms | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.060s | 2.237ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.282m | 9.148ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.280s | 167.243us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.570s | 1.148ms | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.060s | 2.237ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 121 | 276 | 43.84 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 3.470s | 3.649ms | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 20.140s | 1.167ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 10.500s | 5.493ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 304 | 512 | 59.38 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 26 | 92.86 |
| V2 | 18 | 16 | 8 | 44.44 |
| V2S | 10 | 2 | 2 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 78.32 | 93.71 | 78.85 | 87.05 | 73.08 | 82.50 | 98.42 | 34.62 |
UVM_ERROR (jtag_dmi_monitor.sv:136) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 48 failures:
Test rv_dm_jtag_dmi_debug_disabled has 1 failures.
0.rv_dm_jtag_dmi_debug_disabled.19323400027834214729182363772846680264251204909532950648451885851080659826773
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_debug_disabled/latest/run.log
UVM_ERROR @ 16735495 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 16735495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 28 failures.
1.rv_dm_stress_all_with_rand_reset.115209100719663864884004942860342166195346016685239215280492349312939718812027
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7566542 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 7566542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_stress_all_with_rand_reset.24534892079160721042300619612307311026536950315104802304212812055500785740626
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10890126 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 10890126 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.
Test rv_dm_stress_all has 19 failures.
6.rv_dm_stress_all.27940994601403695624062023013489652382642128006877016853717033414084581690486
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2041113574 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 2041113574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_stress_all.103130431034803179158595293156662149981719555608913450722686116286572035785708
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 26041272 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 26041272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:250) [scoreboard] Check failed sba_item.rdata[*] == data (* [*] vs * [*]) has 36 failures:
0.rv_dm_bad_sba_tl_access.68867866765817947242785082532673291695277025267652119785101805923977176006216
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 70586771 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 1606465502 [0x5fc0b7de])
SBA item:
item: (sba_access_item@5384) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'hae5e0b48 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5328) { a_addr: 'hae5e0b48 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h25daa d_param: 'h0 d_source: 'h0 d_data: 'h5fc0b7de d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd64 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
1.rv_dm_bad_sba_tl_access.3844831412394080967323013823770478820882991715260515698995434423840685918046
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 84957779 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 63830 [0xf956])
SBA item:
item: (sba_access_item@7456) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'hcdc724fa wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@7400) { a_addr: 'hcdc724f8 a_data: 'h9cda0000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h2535a d_param: 'h0 d_source: 'h0 d_data: 'hf9562151 d_size: 'h2 d_opcode: 'h1 d_error: 'h1 d_sink: 'h1 d_user: 'he86 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 4 more failures.
1.rv_dm_sba_tl_access.64025188759077604641128107143232184205930987875673217005583655625816856958628
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 37145201 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 1246765694 [0x4a50227e])
SBA item:
item: (sba_access_item@5384) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h8803db98 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5328) { a_addr: 'h8803db98 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h262aa d_param: 'h0 d_source: 'h0 d_data: 'h4a50227e d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd56 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
2.rv_dm_sba_tl_access.16423867839956737312881420949607334067019935598020313071726628299823180548869
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 74879980 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 51864 [0xca98])
SBA item:
item: (sba_access_item@5914) { bus_op: BusOpRead size: SbaAccessSize16b addr: 'haa5cb1e wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5824) { a_addr: 'haa5cb1c a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h2732a d_param: 'h0 d_source: 'h0 d_data: 'hca984c85 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd55 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 13 more failures.
1.rv_dm_delayed_resp_sba_tl_access.45807282175871425150086992527043236015242263960848830664673850259207720203005
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 78692871 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 1845688670 [0x6e02f95e])
SBA item:
item: (sba_access_item@5384) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'h0 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5328) { a_addr: 'h0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'h0 d_data: 'h6e02f95e d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd3a a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
4.rv_dm_delayed_resp_sba_tl_access.104725963013843518917447071594432349316287188712669328281938223705028156030797
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 94425607 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 10305749 [0x9d40d5])
SBA item:
item: (sba_access_item@7510) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'hfb059561 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@7420) { a_addr: 'hfb059560 a_data: 'hb155d900 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h27cce d_param: 'h0 d_source: 'h0 d_data: 'h9d40d504 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd7c a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 10 more failures.
4.rv_dm_autoincr_sba_tl_access.87887506827290619350440235795532920031728445764031269590226439536985354608533
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 26733474 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 3147671636 [0xbb9da854])
SBA item:
item: (sba_access_item@5384) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h51afa4a8 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5328) { a_addr: 'h51afa4a8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h2782a d_param: 'h0 d_source: 'h0 d_data: 'hbb9da854 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd47 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
7.rv_dm_autoincr_sba_tl_access.4516530286759385531676203960090724234306380983327132729880106993766985043100
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 30145613 ps: (rv_dm_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed sba_item.rdata[0] == data (0 [0x0] vs 1561400791 [0x5d1115d7])
SBA item:
item: (sba_access_item@5384) { bus_op: BusOpRead size: SbaAccessSize8b addr: 'h0 wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'h0 } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5328) { a_addr: 'h0 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h247aa d_param: 'h0 d_source: 'h0 d_data: 'h5d1115d7 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h1 d_user: 'hd4c a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
... and 1 more failures.
UVM_ERROR (sba_access_monitor.sv:152) [m_sba_access_monitor] Check failed sberror ==gmv(jtag_dmi_ral.sbcs.sberror) (* [] vs * [])` has 20 failures:
Test rv_dm_autoincr_sba_tl_access has 7 failures.
1.rv_dm_autoincr_sba_tl_access.49662731664312725460132550035364784587802458650966353078590697628354720697883
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 32225956 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 32225956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_autoincr_sba_tl_access.103795982338025241733034057498361899938406191657385508919931843662566581972619
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 52845676 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 52845676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Test rv_dm_bad_sba_tl_access has 11 failures.
3.rv_dm_bad_sba_tl_access.57910402352148959536504609963510181896474890677542796575248974870107629844842
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 14018008 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 3 [0x3])
UVM_INFO @ 14018008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_bad_sba_tl_access.56095679572524189627660485153768370972371788246287947530788319563694558021814
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 71549888 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (0 [0x0] vs 4 [0x4])
UVM_INFO @ 71549888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
6.rv_dm_delayed_resp_sba_tl_access.75092118425878985202080228947207377252133864203236011646163671821278567207325
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 85941029 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (3 [0x3] vs 0 [0x0])
UVM_INFO @ 85941029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_sba_tl_access has 1 failures.
11.rv_dm_sba_tl_access.104997236100182212652620357518861158984921094328504138945222279079152124504117
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 65103857 ps: (sba_access_monitor.sv:152) [uvm_test_top.env.m_sba_access_monitor] Check failed sberror == `gmv(jtag_dmi_ral.sbcs.sberror) (3 [0x3] vs 0 [0x0])
UVM_INFO @ 65103857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_dmi_monitor.sv:91) m_jtag_dmi_monitor [m_jtag_dmi_monitor] JTAG operation * != DmiOpNone in quiet period has 16 failures:
Test rv_dm_halt_resume_whereto has 2 failures.
0.rv_dm_halt_resume_whereto.52062088168414148392722607429029936719013918102539756658516900230956471757282
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_halt_resume_whereto/latest/run.log
UVM_ERROR @ 32972683 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 32972683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_halt_resume_whereto.21253566461258401207815188975784134689088350814833991914372081734038349038602
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_halt_resume_whereto/latest/run.log
UVM_ERROR @ 26849123 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 26849123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 10 failures.
5.rv_dm_stress_all.27266265311505766853416090930212833146505523148843932493612029392411741504374
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 688841817 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 688841817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all.26280443994473140694593425303305528518914273736519222187223493847785049578169
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 50513990 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 50513990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
Test rv_dm_stress_all_with_rand_reset has 4 failures.
27.rv_dm_stress_all_with_rand_reset.15714325336364203599922602057558747684223178042765009539300725029782646515299
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 75934001 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 75934001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.rv_dm_stress_all_with_rand_reset.34775213134552556897748852263033964691180092872759748164289899708377474446725
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 654886346 ps: (jtag_dmi_monitor.sv:91) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] JTAG operation 1 != DmiOpNone in quiet period
UVM_INFO @ 654886346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to write csr jtag_dmi_ral.dmcontrol has 15 failures:
0.rv_dm_stress_all_with_rand_reset.25007818243699963284015627482681863656006228595424305389273161712010804119042
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 13687998 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 13687998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_stress_all_with_rand_reset.29439036004402665816889747091055070148084070980128534781555802751250758919793
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9022110 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 9022110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
13.rv_dm_stress_all.77167923035077222515127133297830452523593351537983529605727257733954669149477
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 24320643 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 24320643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.rv_dm_stress_all.19776546808306260680053435187614862987479177996693083193524091842817861143908
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 25656495 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 25656495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 12 failures:
3.rv_dm_tap_fsm_rand_reset.41555206310852855906854015119496840562339305605597962133745287143630904368580
Line 352, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 14696943989 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 14696943989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_tap_fsm_rand_reset.23514316236712188167928945603019298369768053723069463829895406863323943626041
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 71490738 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 71490738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 9 failures:
0.rv_dm_tap_fsm_rand_reset.108888994019883416496658616246061011309623458420194527964368136657332344290886
Line 272, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 2292551920 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2292551920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_tap_fsm_rand_reset.57479324647995173025409526946890559969578495774510924238430456036086110534459
Line 295, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 4448568024 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 4448568024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 7 failures:
1.rv_dm_stress_all.109035668159692855709133961786865326005738708087993311918681574856172572727560
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 223768169 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 223768169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.rv_dm_stress_all.12371782977419926720605565500301712575348849280364869403931858672284392875199
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 237902626 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (566935683084 [0x840000000c] vs 4209 [0x1071])
UVM_INFO @ 237902626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
3.rv_dm_stress_all_with_rand_reset.112681741333360513188073394395512204709225000473852714210871906185730007625270
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 55601473 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 55601473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_stress_all_with_rand_reset.114239253102963892203074859007939808893202907962552194761283521829248657241095
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 102847542 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (17 [0x11] vs 4209 [0x1071])
UVM_INFO @ 102847542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 6 failures:
Test rv_dm_jtag_dmi_csr_bit_bash has 1 failures.
0.rv_dm_jtag_dmi_csr_bit_bash.18722386110167990503388455366162324687252194242810647446616817149281709318444
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_jtag_dtm_idle_hint has 2 failures.
0.rv_dm_jtag_dtm_idle_hint.5027133398899680858978723869563360902758009106219643416681948569613877667731
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_jtag_dtm_idle_hint.115356317655633266615654057009779127502132193779372042761043884448559510049315
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
2.rv_dm_stress_all.17927969943256048045289147655569899854546383311025686726795175500840946458081
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_tap_fsm_rand_reset has 1 failures.
12.rv_dm_tap_fsm_rand_reset.4602044274850664991335549810537314464642350148704667377264366133757321051740
Line 403, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_autoincr_sba_tl_access has 1 failures.
15.rv_dm_autoincr_sba_tl_access.54905843794935114788203295760206325826588179292315718402966235993205204370295
Line 515, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:280) [scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (* [*] vs * [*]) has 5 failures:
2.rv_dm_autoincr_sba_tl_access.57419052560869028643198658250759195348487552499964912730938887389910618504371
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 117882016 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 117882016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_autoincr_sba_tl_access.110213815504296844543568730004850696882532870399574013275346603589953908167045
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 95932844 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 95932844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
4.rv_dm_bad_sba_tl_access.6232490573910276458045305978771847772660986373189319447018358632927589931070
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 119912961 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 119912961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.rv_dm_bad_sba_tl_access.112989369475072741825599790633522269646799187880752420146378972442746214671014
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 41624734 ps: (rv_dm_scoreboard.sv:280) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrOther (0 [0x0] vs 7 [0x7])
UVM_INFO @ 41624734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:
10.rv_dm_tap_fsm_rand_reset.86916226844013291553710397950370974454234480042827419056762698805942394673656
Line 290, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 4889180844 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 4889180844 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_tap_fsm_rand_reset.15223318452200149672131435862133646513449612017274015130273126988174613499044
Line 290, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 4119944969 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 4119944969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 3 failures:
25.rv_dm_stress_all.54461403292564390773193720297946634694564524633969762406316208241606235284649
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 2588743367 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x50bdf100)
UVM_INFO @ 2588743367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.rv_dm_stress_all.49989336040937165843328903140381171065782147823930341355892402439974496572453
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 3921740562 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xe8c68100)
UVM_INFO @ 3921740562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:240) [scoreboard] Check failed word_aligned_addr == sba_tl_item.a_addr (* [*] vs * [*]) has 2 failures:
Test rv_dm_delayed_resp_sba_tl_access has 1 failures.
0.rv_dm_delayed_resp_sba_tl_access.111585838942892243866391731873670855376840605516865300842932483590988060406302
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 87034746 ps: (rv_dm_scoreboard.sv:240) [uvm_test_top.env.scoreboard] Check failed word_aligned_addr == sba_tl_item.a_addr (1352489908 [0x509d5bb4] vs 3180854672 [0xbd97fd90])
SBA item:
item: (sba_access_item@6904) { bus_op: BusOpWrite size: SbaAccessSize16b addr: 'h509d5bb4 wdata: { [0]: 'h24add021 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6586) { a_addr: 'hbd97fd90 a_data: 'h83000000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h25147 d_param: 'h0 d_source: 'h0 d_data: 'h61161a09 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd18 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Test rv_dm_autoincr_sba_tl_access has 1 failures.
17.rv_dm_autoincr_sba_tl_access.114325554214449208648164705264157141622582172825635307296184739499003361837568
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 26973725 ps: (rv_dm_scoreboard.sv:240) [uvm_test_top.env.scoreboard] Check failed word_aligned_addr == sba_tl_item.a_addr (458820364 [0x1b590b0c] vs 458820368 [0x1b590b10])
SBA item:
item: (sba_access_item@5910) { bus_op: BusOpRead size: SbaAccessSize32b addr: 'h1b590b0c wdata: - readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: { [0]: 'hed5ca89b } is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5520) { a_addr: 'h1b590b10 a_data: 'h27769e11 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h278a0 d_param: 'h0 d_source: 'h0 d_data: 'h5bc44e07 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd74 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (rv_dm_scoreboard.sv:282) [scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (* [*] vs * [*]) has 2 failures:
0.rv_dm_autoincr_sba_tl_access.2794589856770431548846682111987838414755430483750303926669501510003529928858
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 45524846 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 45524846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_autoincr_sba_tl_access.97910940414857257715606056154969790124621042314266182453971506953183808739223
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 15855015 ps: (rv_dm_scoreboard.sv:282) [uvm_test_top.env.scoreboard] Check failed sba_item.is_err == jtag_rv_debugger_pkg::SbaErrBadAddr (0 [0x0] vs 2 [0x2])
UVM_INFO @ 15855015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:260) [scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (* [*] vs * [*]) has 2 failures:
Test rv_dm_sba_tl_access has 1 failures.
6.rv_dm_sba_tl_access.5587524429862322410084757231321048449399352231548981071904683018749656858671
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 16856816 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (4 [0x4] vs 1 [0x1])
SBA item:
item: (sba_access_item@5824) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h50e8fe2 wdata: { [0]: 'hcba6c6e9 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5686) { a_addr: 'h50e8fe0 a_data: 'h3b30000 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h4 a_user: 'h26378 d_param: 'h0 d_source: 'h0 d_data: 'h2b3a600e d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd63 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Test rv_dm_autoincr_sba_tl_access has 1 failures.
14.rv_dm_autoincr_sba_tl_access.14229980398015858896030826078810717155839211658756572888976451017273399362955
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 66670653 ps: (rv_dm_scoreboard.sv:260) [uvm_test_top.env.scoreboard] Check failed sba_tl_item.a_opcode == tlul_pkg::PutPartialData (0 [0x0] vs 1 [0x1])
SBA item:
item: (sba_access_item@6012) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'heca2bdcc wdata: { [0]: 'h3e390917 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@5956) { a_addr: 'heca2bdcc a_data: 'h3e390917 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h24597 d_param: 'h0 d_source: 'h0 d_data: 'h8192a567 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h0 d_user: 'h1c82 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 2 failures:
9.rv_dm_stress_all_with_rand_reset.110020061843678294210014893515767933257535448553843929227020793510467332219422
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 177635203 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 177635203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.rv_dm_stress_all_with_rand_reset.21544196729509677077034294064126836362367416387690443678055795442412874989018
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1993229602 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 1993229602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:275) [scoreboard] Check failed byte_mask == sba_tl_item.a_mask (* [*] vs * [*]) has 2 failures:
Test rv_dm_sba_tl_access has 1 failures.
13.rv_dm_sba_tl_access.75628163777037498332150125023845355733420644574024663880279194213294523370630
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 116855130 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (4 [0x4] vs 12 [0xc])
SBA item:
item: (sba_access_item@7052) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hf3a67de2 wdata: { [0]: 'h1304e9a4 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@7014) { a_addr: 'hf3a67de0 a_data: 'he9a40000 a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h26310 d_param: 'h0 d_source: 'h0 d_data: 'h13ea66a5 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h1 d_user: 'h1cb7 a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Test rv_dm_autoincr_sba_tl_access has 1 failures.
19.rv_dm_autoincr_sba_tl_access.110345642696275123533320888721718853464711607043895908450214480888971699093511
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 221258465 ps: (rv_dm_scoreboard.sv:275) [uvm_test_top.env.scoreboard] Check failed byte_mask == sba_tl_item.a_mask (4 [0x4] vs 12 [0xc])
SBA item:
item: (sba_access_item@6640) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h24d296e wdata: { [0]: 'hda49d867 } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
SBA TL item:
req: (cip_tl_seq_item@6584) { a_addr: 'h24d296c a_data: 'hd8670000 a_mask: 'hc a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h1 a_user: 'h2448a d_param: 'h0 d_source: 'h0 d_data: 'h24fd8db3 d_size: 'h2 d_opcode: 'h0 d_error: 'h0 d_sink: 'h1 d_user: 'h1cbd a_source_is_overridden: 'h0 a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 2 failures:
Test rv_dm_stress_all_with_rand_reset has 1 failures.
18.rv_dm_stress_all_with_rand_reset.224845905324823147275481389502769537885239437461739628849152209118675169634
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 68810409 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (14 [0xe] vs 0 [0x0])
UVM_INFO @ 68810409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 1 failures.
21.rv_dm_stress_all.6838397797764190909152993783119023400456534250301771511117154602888132236762
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/21.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 4066880368 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (4 [0x4] vs 2958143569 [0xb051b051])
UVM_INFO @ 4066880368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*]) has 2 failures:
32.rv_dm_tap_fsm_rand_reset.34175542827529330070860954926793191509961988732224112538505538391930726629719
Line 304, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 4555709512 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 4555709512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.rv_dm_tap_fsm_rand_reset.88576910334164103589633960752070663504469412010750024166724628986997763050255
Line 311, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 6990160351 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 6990160351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:54) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 1 failures:
0.rv_dm_stress_all.51684943947359371193262825212451329400371524312381477477528183904695154255094
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 4218872590 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 4218872590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:193) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@6116) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * } has 1 failures:
2.rv_dm_delayed_resp_sba_tl_access.113504516616378158416772215184196605112892084870789671083211504850408311530719
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 186797632 ps: (rv_dm_scoreboard.sv:193) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@6116) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'h51474fff wdata: { [0]: 'h988f3a2c } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 186797632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:74) [scoreboard] Check failed item.dout == * (* [*] vs * [*]) has 1 failures:
3.rv_dm_stress_all.2102880792756936181866321297555466073971424980225912039613965019100498501103
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 2781881162 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (1111382043776 [0x102c3882c80] vs 0 [0x0])
UVM_INFO @ 2781881162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 1 failures:
4.rv_dm_stress_all_with_rand_reset.81567409674441520835570047699462539422976528287201309106711487766412842042084
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 65133231 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 65133231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sba_access_monitor.sv:178) [m_sba_access_monitor] Check failed dmi_item.rdata == exp_addr (* [*] vs * [*]) has 1 failures:
10.rv_dm_autoincr_sba_tl_access.108681069803845292150820377386512903480515309809375331943753539337575549581459
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 288750613 ps: (sba_access_monitor.sv:178) [uvm_test_top.env.m_sba_access_monitor] Check failed dmi_item.rdata == exp_addr (306811840 [0x124993c0] vs 306811836 [0x124993bc])
UVM_INFO @ 288750613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
12.rv_dm_stress_all.37054977803314395914934656589207701263082466671397572492195078244551746538022
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
Job ID: smart:3df28853-99fe-4b6f-960d-f0b105f2098f
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 1 failures:
14.rv_dm_stress_all_with_rand_reset.33074670851067546452794543416109109914344699643713347886213250634008306519210
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 351880763 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (29 [0x1d] vs 4616989 [0x46731d])
UVM_INFO @ 351880763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:193) scoreboard [scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@6356) { bus_op: BusOpWrite size: SbaAccessSize8b addr: * wdata: { [*]: * } readonaddr: 'hX readondata: 'hX autoincrement: * rdata: - is_busy_err: * is_err: SbaErrNone timed_out: * } has 1 failures:
15.rv_dm_delayed_resp_sba_tl_access.24609587274037422594784000832136823207269501841750490483255371307646912103966
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 214409619 ps: (rv_dm_scoreboard.sv:193) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Received predicted SBA access but no transaction was seen on the SBA TL host interface: item: (sba_access_item@6356) { bus_op: BusOpWrite size: SbaAccessSize8b addr: 'hbab195f7 wdata: { [0]: 'h2406936c } readonaddr: 'hX readondata: 'hX autoincrement: 'h0 rdata: - is_busy_err: 'h0 is_err: SbaErrNone timed_out: 'h0 }
UVM_INFO @ 214409619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 1 failures:
15.rv_dm_stress_all_with_rand_reset.26236980471623292981031383558087823091123417240114820375275185933042061938302
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 472222784 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (0 [0x0] vs 3350242706 [0xc7b0a592])
UVM_INFO @ 472222784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sba_access_monitor.sv:142) [m_sba_access_monitor] Check failed sbbusyerror ==gmv(jtag_dmi_ral.sbcs.sbbusyerror) (* [] vs * [])` has 1 failures:
17.rv_dm_sba_tl_access.70252177579795132199527073425209745038266036360797322203596229711315647889963
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 244275045 ps: (sba_access_monitor.sv:142) [uvm_test_top.env.m_sba_access_monitor] Check failed sbbusyerror == `gmv(jtag_dmi_ral.sbcs.sbbusyerror) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 244275045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:59) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*]) has 1 failures:
23.rv_dm_tap_fsm_rand_reset.42802304985772843015837738515928058229980133996149642689467495001210225890969
Line 382, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 15393630023 ps: (rv_dm_smoke_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 15393630023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*) has 1 failures:
31.rv_dm_tap_fsm_rand_reset.102558160995133834410511638229133055178518536903394585538239355243833877690693
Line 304, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 6817654506 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 6817654506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to read csr/field jtag_dmi_ral.abstractdata_* has 1 failures:
34.rv_dm_stress_all.71686680380623290871709079288541199447717172331195633624144546074199562920761
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3421544485 ps: (csr_utils_pkg.sv:371) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to read csr/field jtag_dmi_ral.abstractdata_0
UVM_INFO @ 3421544485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:167) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 1 failures:
47.rv_dm_stress_all_with_rand_reset.33440644746285422813321358897335240417038631820043884784269025276766882206288
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 6969144055 ps: (rv_dm_base_vseq.sv:167) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 6969144055 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---