RV_DM Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 2.130s 445.491us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 1.070s 117.611us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.900s 89.674us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 13.910s 4.427ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 0.820s 94.261us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 2.690s 2.458ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 3.300s 836.764us 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.448m 50.000ms 4 5 80.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 57.170s 16.545ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 6.180s 2.343ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 4.630s 6.682ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 1.590s 310.630us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 3.150s 969.942us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 1.220s 173.268us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.580s 280.977us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.780s 112.069us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 0.750s 32.973us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 1.490s 236.903us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.910s 76.771us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.850s 141.598us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 1.590s 310.630us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.820s 74.667us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.280s 167.243us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.570s 1.148ms 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.188m 8.134ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.282m 9.148ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 9.510s 3.823ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.282m 9.148ms 5 5 100.00
rv_dm_csr_rw 2.570s 1.148ms 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.720s 61.550us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.780s 27.218us 5 5 100.00
V1 TOTAL 158 161 98.14
V2 idcode rv_dm_smoke 2.130s 445.491us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 2.750s 1.171ms 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.302m 50.000ms 0 2 0.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.010s 110.389us 2 2 100.00
V2 sba rv_dm_sba_tl_access 7.370s 2.747ms 1 20 5.00
rv_dm_delayed_resp_sba_tl_access 6.240s 3.217ms 4 20 20.00
V2 bad_sba rv_dm_bad_sba_tl_access 3.860s 1.080ms 1 20 5.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 20.660s 50.000ms 0 20 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.800s 62.815us 1 2 50.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 1.450s 1.710ms 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 0.900s 82.583us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 4.500s 3.908ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 44.940s 12.487ms 11 40 27.50
V2 stress_all rv_dm_stress_all 2.993h 10.000s 1 50 2.00
V2 alert_test rv_dm_alert_test 0.840s 33.133us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.850s 695.818us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.850s 695.818us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.282m 9.148ms 5 5 100.00
rv_dm_csr_hw_reset 2.280s 167.243us 5 5 100.00
rv_dm_csr_rw 2.570s 1.148ms 20 20 100.00
rv_dm_same_csr_outstanding 8.060s 2.237ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.282m 9.148ms 5 5 100.00
rv_dm_csr_hw_reset 2.280s 167.243us 5 5 100.00
rv_dm_csr_rw 2.570s 1.148ms 20 20 100.00
rv_dm_same_csr_outstanding 8.060s 2.237ms 20 20 100.00
V2 TOTAL 121 276 43.84
V2S tl_intg_err rv_dm_sec_cm 3.470s 3.649ms 5 5 100.00
rv_dm_tl_intg_err 20.140s 1.167ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 10.500s 5.493ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 304 512 59.38

Testplan Progress

Items Total Written Passing Progress
V1 28 28 26 92.86
V2 18 16 8 44.44
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
78.32 93.71 78.85 87.05 73.08 82.50 98.42 34.62

Failure Buckets

Past Results