RV_DM Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.960s 606.210us 1 2 50.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.800s 60.841us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.980s 131.942us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 14.500s 4.711ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.140s 289.206us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 5.020s 1.203ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 6.090s 2.525ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 3.704m 79.934ms 5 5 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 38.630s 17.675ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 0.690s 23.080us 0 2 0.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.730s 102.110us 0 2 0.00
V1 cmderr_exception rv_dm_cmderr_exception 0.910s 60.501us 0 2 0.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 0.750s 23.645us 0 2 0.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.700s 8.040us 0 2 0.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 0.770s 61.742us 0 2 0.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.710s 23.537us 0 2 0.00
V1 halt_resume rv_dm_halt_resume_whereto 0.780s 22.513us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 0.720s 18.956us 0 2 0.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.720s 53.674us 0 2 0.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.890s 150.589us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 0.910s 60.501us 0 2 0.00
V1 rom_read_access rv_dm_rom_read_access 0.850s 138.254us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.570s 352.226us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.580s 596.401us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 48.340s 50.000ms 4 5 80.00
V1 csr_aliasing rv_dm_csr_aliasing 1.147m 1.180ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 6.780s 3.310ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.147m 1.180ms 5 5 100.00
rv_dm_csr_rw 2.580s 596.401us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.710s 24.749us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.730s 30.914us 5 5 100.00
V1 TOTAL 139 161 86.34
V2 idcode rv_dm_smoke 1.960s 606.210us 1 2 50.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 0.760s 40.685us 0 2 0.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.810s 92.661us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0.800s 190.179us 0 2 0.00
V2 sba rv_dm_sba_tl_access 0.780s 51.773us 0 20 0.00
rv_dm_delayed_resp_sba_tl_access 1.000s 114.172us 0 20 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 0.820s 64.024us 0 20 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 0.830s 50.590us 0 20 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.710s 45.057us 0 2 0.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 0.770s 47.009us 0 2 0.00
V2 hart_unavail rv_dm_hart_unavail 0.690s 15.394us 0 5 0.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 3.300s 2.805ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 48.610s 15.221ms 12 40 30.00
V2 stress_all rv_dm_stress_all 14.890s 5.401ms 8 50 16.00
V2 alert_test rv_dm_alert_test 0.800s 31.686us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.310s 214.151us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.310s 214.151us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.147m 1.180ms 5 5 100.00
rv_dm_csr_hw_reset 2.570s 352.226us 5 5 100.00
rv_dm_csr_rw 2.580s 596.401us 20 20 100.00
rv_dm_same_csr_outstanding 8.790s 2.536ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.147m 1.180ms 5 5 100.00
rv_dm_csr_hw_reset 2.570s 352.226us 5 5 100.00
rv_dm_csr_rw 2.580s 596.401us 20 20 100.00
rv_dm_same_csr_outstanding 8.790s 2.536ms 20 20 100.00
V2 TOTAL 113 276 40.94
V2S tl_intg_err rv_dm_sec_cm 1.650s 219.871us 5 5 100.00
rv_dm_tl_intg_err 20.020s 4.398ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 12.300s 3.415ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 277 512 54.10

Testplan Progress

Items Total Written Passing Progress
V1 28 28 16 57.14
V2 18 16 5 27.78
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
73.98 90.58 76.37 86.09 58.97 77.00 98.31 30.55

Failure Buckets

Past Results