00fe426038| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 1.960s | 606.210us | 1 | 2 | 50.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0.800s | 60.841us | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0.980s | 131.942us | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 14.500s | 4.711ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 1.140s | 289.206us | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 5.020s | 1.203ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 6.090s | 2.525ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 3.704m | 79.934ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 38.630s | 17.675ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 0.690s | 23.080us | 0 | 2 | 0.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0.730s | 102.110us | 0 | 2 | 0.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0.910s | 60.501us | 0 | 2 | 0.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0.750s | 23.645us | 0 | 2 | 0.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0.700s | 8.040us | 0 | 2 | 0.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 0.770s | 61.742us | 0 | 2 | 0.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.710s | 23.537us | 0 | 2 | 0.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 0.780s | 22.513us | 0 | 2 | 0.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 0.720s | 18.956us | 0 | 2 | 0.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 0.720s | 53.674us | 0 | 2 | 0.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 0.890s | 150.589us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 0.910s | 60.501us | 0 | 2 | 0.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.850s | 138.254us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.570s | 352.226us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.580s | 596.401us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 48.340s | 50.000ms | 4 | 5 | 80.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.147m | 1.180ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 6.780s | 3.310ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.147m | 1.180ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.580s | 596.401us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.710s | 24.749us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.730s | 30.914us | 5 | 5 | 100.00 |
| V1 | TOTAL | 139 | 161 | 86.34 | |||
| V2 | idcode | rv_dm_smoke | 1.960s | 606.210us | 1 | 2 | 50.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 0.760s | 40.685us | 0 | 2 | 0.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0.810s | 92.661us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0.800s | 190.179us | 0 | 2 | 0.00 |
| V2 | sba | rv_dm_sba_tl_access | 0.780s | 51.773us | 0 | 20 | 0.00 |
| rv_dm_delayed_resp_sba_tl_access | 1.000s | 114.172us | 0 | 20 | 0.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 0.820s | 64.024us | 0 | 20 | 0.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 0.830s | 50.590us | 0 | 20 | 0.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0.710s | 45.057us | 0 | 2 | 0.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0.770s | 47.009us | 0 | 2 | 0.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 0.690s | 15.394us | 0 | 5 | 0.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 3.300s | 2.805ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 48.610s | 15.221ms | 12 | 40 | 30.00 | ||
| V2 | stress_all | rv_dm_stress_all | 14.890s | 5.401ms | 8 | 50 | 16.00 |
| V2 | alert_test | rv_dm_alert_test | 0.800s | 31.686us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 5.310s | 214.151us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 5.310s | 214.151us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.147m | 1.180ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.570s | 352.226us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.580s | 596.401us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.790s | 2.536ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.147m | 1.180ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.570s | 352.226us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.580s | 596.401us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 8.790s | 2.536ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 113 | 276 | 40.94 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 1.650s | 219.871us | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 20.020s | 4.398ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 12.300s | 3.415ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 277 | 512 | 54.10 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 16 | 57.14 |
| V2 | 18 | 16 | 5 | 27.78 |
| V2S | 10 | 2 | 2 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 73.98 | 90.58 | 76.37 | 86.09 | 58.97 | 77.00 | 98.31 | 30.55 |
UVM_ERROR (rv_dm_scoreboard.sv:83) [scoreboard] Check failed rwdata == * (* [*] vs * [*]) has 136 failures:
Test rv_dm_smoke has 1 failures.
0.rv_dm_smoke.84870742088009375825207263754532667512828374039678174179630557058837780359764
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log
UVM_ERROR @ 9518917 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 9518917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_sba_tl_access has 19 failures.
0.rv_dm_sba_tl_access.8502439726640762301380787514166659309983834173832234452610734858249091596351
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 63631356 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 63631356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_sba_tl_access.111357410918536831828108443802392750206621628157953208946365282493927934387261
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 18796199 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 18796199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 17 more failures.
Test rv_dm_delayed_resp_sba_tl_access has 20 failures.
0.rv_dm_delayed_resp_sba_tl_access.99221878340795121114089221040385180262628235378276116377199280831229339168340
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 45984186 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 45984186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_delayed_resp_sba_tl_access.26804766501751169903839944989976501472039958903208619941958064795288306930938
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_ERROR @ 56776873 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 56776873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_bad_sba_tl_access has 20 failures.
0.rv_dm_bad_sba_tl_access.115231724157120934086331117464949773093639282891885746770520550225325961872605
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 12333782 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 12333782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_bad_sba_tl_access.25716054254259791173431667198194516883457508868295268260918761381093812845679
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_bad_sba_tl_access/latest/run.log
UVM_ERROR @ 49885010 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 49885010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
Test rv_dm_autoincr_sba_tl_access has 17 failures.
0.rv_dm_autoincr_sba_tl_access.85584240674065526309487767712671146671357201371322006638804153174526082567015
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 67572441 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 67572441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_autoincr_sba_tl_access.54032337256083632235897665675896065981433674033061448856897697779694307441524
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 8652350 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 8652350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
... and 17 more tests.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 12 failures:
3.rv_dm_stress_all.77034777279742957527193409559654361587897948980684713891531339387416414830265
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 38030409 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (444767946 [0x1a829eca] vs 3999322939 [0xee60d33b])
UVM_INFO @ 38030409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all.29063887064303511866097223320765982627372022521478367591953454858319099914504
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1192188709 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (4270342142 [0xfe883ffe] vs 0 [0x0])
UVM_INFO @ 1192188709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
5.rv_dm_stress_all_with_rand_reset.82411539600067222515942447237818308336154757270009015545314524171106850589634
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 65427803 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (444767946 [0x1a829eca] vs 409694101 [0x186b6f95])
UVM_INFO @ 65427803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.rv_dm_stress_all_with_rand_reset.16864794073980124255973878728837376260557974266184760972073416707704578292709
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 80437699 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (196699215 [0xbb9644f] vs 0 [0x0])
UVM_INFO @ 80437699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 10 failures:
0.rv_dm_tap_fsm_rand_reset.49250626296298624116280152611833906837402492677072036431174663051963752403004
Line 341, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 24784902926 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 24784902926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_tap_fsm_rand_reset.37795575670489919077174206044147600795287640871327883446265512489265021352397
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 2289042223 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2289042223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 7 failures:
1.rv_dm_tap_fsm_rand_reset.31314166345701103282964440843921317351231224483971561537555460774869206502196
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 801113275 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 801113275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.rv_dm_tap_fsm_rand_reset.48311543299378535548486253997897484754551069233306270853014599311319524597649
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 91231590 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 91231590 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:74) [scoreboard] Check failed item.dout == * (* [*] vs * [*]) has 6 failures:
Test rv_dm_autoincr_sba_tl_access has 3 failures.
1.rv_dm_autoincr_sba_tl_access.27251269973235744728557545454352354993319983787149892670555504370415154495073
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 6866207 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (274877906948 [0x4000000004] vs 0 [0x0])
UVM_INFO @ 6866207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.rv_dm_autoincr_sba_tl_access.20778124755620621200826871015145105907140265622031816278465389430002549141417
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 13742168 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (274877906948 [0x4000000004] vs 0 [0x0])
UVM_INFO @ 13742168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test rv_dm_sba_tl_access has 1 failures.
10.rv_dm_sba_tl_access.82346663790591468797791700770091508269144718271797709776768623448082415569882
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 11428193 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (274877906948 [0x4000000004] vs 0 [0x0])
UVM_INFO @ 11428193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
32.rv_dm_stress_all_with_rand_reset.55781419800727309392187428366201515411125858169605592419604402213349755349425
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11333940 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (274877906948 [0x4000000004] vs 0 [0x0])
UVM_INFO @ 11333940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
37.rv_dm_stress_all_with_rand_reset.77292974188096336867286496690888570014561866983801044833198783994652650275518
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/37.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 12895965 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (274877906948 [0x4000000004] vs 0 [0x0])
UVM_INFO @ 12895965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*]) has 6 failures:
6.rv_dm_stress_all_with_rand_reset.20605601091667513992236967722163317668868797601913357478316455785442953428010
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 386715254 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 386715254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_dm_stress_all_with_rand_reset.74591263921260319694754161679106673650031009858919447831562162792956365646403
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 66305420 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 66305420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
42.rv_dm_stress_all.37933241607788771915380042843438276044135158752647685096880133802084032414611
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 151813419 ps: (rv_dm_hart_unavail_vseq.sv:24) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 151813419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:198) [rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 5 failures:
2.rv_dm_stress_all.75718393502320978375446348571558634536110685553898808227433103558816562715155
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1340357683 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1340357683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_stress_all.83367288036346459103601123003258921309206418951000930050957573405941210898885
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 12770491 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12770491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
12.rv_dm_stress_all_with_rand_reset.13074288252517466982665157090354195135417358753289319003800444234640190005691
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 45804906 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 45804906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
44.rv_dm_stress_all_with_rand_reset.19947806573460287465444148812758995967311130141818807624474642858026168222087
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/44.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 10590657 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 10590657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 4 failures:
1.rv_dm_stress_all.43811262669160745736478447505849420757063603929544089474392925221925630445855
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 98899776 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (7 [0x7] vs 444767946 [0x1a829eca])
UVM_INFO @ 98899776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
28.rv_dm_stress_all.44026188330180912747023426770627747030214265502123897900475340138117874183773
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 80821668 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (8 [0x8] vs 444767946 [0x1a829eca])
UVM_INFO @ 80821668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
8.rv_dm_stress_all_with_rand_reset.114716905213880793241332921418891210976480669068032341550579326663139615686286
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 39552303 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (26 [0x1a] vs 0 [0x0])
UVM_INFO @ 39552303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:198) [rv_dm_halt_resume_whereto_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 4 failures:
2.rv_dm_stress_all_with_rand_reset.66981679873519619537631276661991060656421628356414743208415879236146696448283
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 20747440 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 20747440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.rv_dm_stress_all_with_rand_reset.31620048136617064683290724240403950790399910185834999243310593453978417753238
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/19.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11366466 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 11366466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
38.rv_dm_stress_all.48931143744938916410101000853980528818337729333907382648337841275253625812166
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 28857522 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 28857522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=*) has 4 failures:
6.rv_dm_tap_fsm_rand_reset.19573437768583512764193995312525826218908313098696479745413339746815811941913
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 4301383296 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 4301383296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_tap_fsm_rand_reset.85320766349658010282973610081776980350569120525366293676826291078206687636794
Line 293, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_FATAL @ 5634569899 ps: (csr_utils_pkg.sv:378) [csr_utils::csr_rd] Timeout waiting to csr_rd jtag_dtm_ral.idcode (addr=0x1)
UVM_INFO @ 5634569899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:87) [scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (* [*] vs * [*]) has 4 failures:
15.rv_dm_stress_all.77198479989771558654489848007801038143908248504127406862834057133581097416906
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/15.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 4009306419 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (8 [0x8] vs 1779071784 [0x6a0a7b28])
UVM_INFO @ 4009306419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rv_dm_stress_all.84395992738431313032144197743170963738885784284037054453315470334192288759534
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 6312071000 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (8 [0x8] vs 1779071784 [0x6a0a7b28])
UVM_INFO @ 6312071000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
24.rv_dm_stress_all_with_rand_reset.65107310898123546375381995351192069602061864128922933472187038721372618507966
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 154784370 ps: (rv_dm_scoreboard.sv:87) [uvm_test_top.env.scoreboard] Check failed item.dout == selected_dtm_csr.get_mirrored_value() (8 [0x8] vs 1779071784 [0x6a0a7b28])
UVM_INFO @ 154784370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:198) [rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 4 failures:
Test rv_dm_stress_all has 2 failures.
17.rv_dm_stress_all.111418983547993423240662494668380691693402009923015036213686046661646366236881
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 7045006 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 7045006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.rv_dm_stress_all.42866457585273422268041849804955304696446112762608628264167762432094546640771
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 22021184 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 22021184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
20.rv_dm_stress_all_with_rand_reset.40865990244494973805345590538507141492294649655283368809815382411189158681322
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 21878413 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21878413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.rv_dm_stress_all_with_rand_reset.44472876375801242511550851988813920442866784241909428792751697459018561243245
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 40917202 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 40917202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:
30.rv_dm_tap_fsm_rand_reset.8276368462389627898063836241547345843080277751615608001510165711581569060150
Line 265, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 467667654 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 467667654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.rv_dm_tap_fsm_rand_reset.43437691949707514755391747309044313078636325745503246746080157717147194646557
Line 304, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 5973455588 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 5973455588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:198) [rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 3 failures:
0.rv_dm_stress_all_with_rand_reset.32579752065186439260056459234165799960069975593993707480863494724367412341824
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 42428218 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 42428218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.rv_dm_stress_all_with_rand_reset.43031869548310533946272408167767384991023472693676578522737295566614019046093
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9225968 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 9225968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 3 failures:
Test rv_dm_stress_all_with_rand_reset has 1 failures.
1.rv_dm_stress_all_with_rand_reset.4481427496340745661500591378710024356872045524177756054877840985991558749227
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 3414765626 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x72687100)
UVM_INFO @ 3414765626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all has 2 failures.
44.rv_dm_stress_all.58265491473059331322680251292256323020552786535366112102684389407013819637421
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/44.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 4743266908 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xdd35d100)
UVM_INFO @ 4743266908 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
47.rv_dm_stress_all.111683782764588365570655473783405005242598477077060559912261870711960365949109
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 2750944273 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0x58dfb100)
UVM_INFO @ 2750944273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:198) [rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 3 failures:
Test rv_dm_stress_all has 2 failures.
14.rv_dm_stress_all.106799535337553866766490476079157310866272266908983913039841795574456780823429
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 33351138 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 33351138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
33.rv_dm_stress_all.79830481654229569101226684934939927377491935634081027747033278411652509463925
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 8213017 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 8213017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
29.rv_dm_stress_all_with_rand_reset.76592546745917609793967322424609281899173400265232033387109171064033073096804
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30618152 ps: (rv_dm_base_vseq.sv:198) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 30618152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:174) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 3 failures:
Test rv_dm_stress_all has 2 failures.
27.rv_dm_stress_all.34231862463884216747708839995092871903601710671564087294664325241658472591119
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/27.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 5981581389 ps: (rv_dm_base_vseq.sv:174) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 2 [0x2])
UVM_INFO @ 5981581389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
41.rv_dm_stress_all.57217821648717572808695138225745495823138934638450502754172763759724007733323
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/41.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 365918351 ps: (rv_dm_base_vseq.sv:174) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 2 [0x2])
UVM_INFO @ 365918351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
45.rv_dm_stress_all_with_rand_reset.9191951562762001519927905650865352457391885420816224372373658242182629787788
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/45.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1526130188 ps: (rv_dm_base_vseq.sv:174) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 1526130188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[*].get_reset() (* [*] vs * [*]) has 2 failures:
4.rv_dm_stress_all_with_rand_reset.61891521983395934803771226948091984082928559157361875997790356888626548506475
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 105106964 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (444767946 [0x1a829eca] vs 0 [0x0])
UVM_INFO @ 105106964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all_with_rand_reset.36127000869601930720645142500443057065631431173956046761014338821571628387431
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 140151188 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (444767946 [0x1a829eca] vs 0 [0x0])
UVM_INFO @ 140151188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:38) [rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == get_field_val(jtag_dmi_ral.dmcontrol.ndmreset, rdata) (* [*] vs * [*]) has 2 failures:
Test rv_dm_stress_all has 1 failures.
18.rv_dm_stress_all.72036741755889009156578603319017157253328576872951084652490997885070672539655
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/18.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 28966602 ps: (rv_dm_ndmreset_req_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == get_field_val(jtag_dmi_ral.dmcontrol.ndmreset, rdata) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 28966602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
28.rv_dm_stress_all_with_rand_reset.64705740360954020580545759290627319493481047368497212516837797953335077955757
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 34368790 ps: (rv_dm_ndmreset_req_vseq.sv:38) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == get_field_val(jtag_dmi_ral.dmcontrol.ndmreset, rdata) (0 [0x0] vs 1 [0x1])
UVM_INFO @ 34368790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_dmi_monitor.sv:136) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 2 failures:
Test rv_dm_stress_all has 1 failures.
20.rv_dm_stress_all.43440948256447565056182642376028107517095276021039256713616928234923225276534
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 5333242767 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 5333242767 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
47.rv_dm_stress_all_with_rand_reset.66250671602277794921744959212742863347580959165137483951547850956260225220798
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/47.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 139069647 ps: (jtag_dmi_monitor.sv:136) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 139069647 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to write csr jtag_dmi_ral.dmcontrol has 2 failures:
22.rv_dm_stress_all.44142097928546725924895382482275754148451760530409283655712443560223032970685
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 20410497 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 20410497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.rv_dm_stress_all.37208783393283925252223148153345426133015769809704263395191631745240926823069
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 4189764 ps: (csr_utils_pkg.sv:247) [csr_utils] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to write csr jtag_dmi_ral.dmcontrol
UVM_INFO @ 4189764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
0.rv_dm_csr_bit_bash.60697623440436637833326765286909229028200841108798862021158425422569044679127
Line 316, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_csr_bit_bash/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:48) [seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (* [*] vs * [*]) has 1 failures:
8.rv_dm_tap_fsm_rand_reset.84379988703865018304403991331276298108171905278035147535737387479232346093053
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 459051630 ps: (rv_dm_smoke_vseq.sv:48) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.anyunavail, data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 459051630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:54) [rv_dm_ndmreset_req_vseq] Check failed rdata == * (* [*] vs * [*]) has 1 failures:
11.rv_dm_stress_all.12930347470325630521064343652966921315227082606146304122714203435362084182910
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3699423114 ps: (rv_dm_ndmreset_req_vseq.sv:54) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed rdata == 'h58710590 (0 [0x0] vs 1483802000 [0x58710590])
UVM_INFO @ 3699423114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:58) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == dm::jal(.rd(0), .imm(prog_buf_addr - whereto_addr)) (* [*] vs * [*]) has 1 failures:
12.rv_dm_stress_all.48882475000388529308149694124472069630525905570476639084485473468627691734494
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/12.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1561112201 ps: (rv_dm_halt_resume_whereto_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == dm::jal(.rd(0), .imm(prog_buf_addr - whereto_addr)) (58720367 [0x380006f] vs 100663407 [0x600006f])
UVM_INFO @ 1561112201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
24.rv_dm_tap_fsm_rand_reset.109130884650066705166561760135935701964214334339940538332389792969346020457249
Line 399, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 15717698919 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 15717698919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:753) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
25.rv_dm_tap_fsm_rand_reset.48249518153285482622851264160879308649114963719873980109303012898625844616291
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 21915987 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 21915987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:32) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == data (* [*] vs * [*]) has 1 failures:
29.rv_dm_stress_all.110317503042919437782237170988154615448049749207611179316793741212813714046848
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 98650759 ps: (rv_dm_smoke_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 98650759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_ndmreset_req_vseq.sv:43) [rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, rdata) (* [*] vs * [*]) has 1 failures:
35.rv_dm_stress_all.87688182431155291930023265057226280590192363660570548561272348338769117450123
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/35.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 202647078 ps: (rv_dm_ndmreset_req_vseq.sv:43) [uvm_test_top.env.virtual_sequencer.rv_dm_ndmreset_req_vseq] Check failed cfg.rv_dm_vif.unavailable == get_field_val(jtag_dmi_ral.dmstatus.allunavail, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 202647078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:40) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (* [*] vs * [*]) has 1 failures:
46.rv_dm_stress_all.78795957815280861252701252769740662035159956528524323164702182057671099885055
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/46.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 380204599 ps: (rv_dm_smoke_vseq.sv:40) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.ndmreset_req == data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 380204599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---