Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
85.64	100.00	55.32	85.38		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	27574102	12354	0	0
late_debug_enable_rd_A	27574102	2381	0	0
late_debug_enable_regwen_rd_A	27574102	1849	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27574102	12354	0	0
T26	539214	25	0	0
T27	919105	117	0	0
T28	252292	50	0	0
T32	18314	1	0	0
T50	741574	161	0	0
T60	644177	33	0	0
T68	105113	43	0	0
T69	7607	281	0	0
T70	7593	383	0	0
T71	5896	809	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27574102	2381	0	0
T26	539214	38	0	0
T27	919105	141	0	0
T28	252292	52	0	0
T60	644177	61	0	0
T61	7614	4	0	0
T72	732095	293	0	0
T74	8212	5	0	0
T77	245644	131	0	0
T82	997526	117	0	0
T112	13069	1	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27574102	1849	0	0
T26	539214	27	0	0
T27	919105	155	0	0
T28	252292	56	0	0
T60	644177	49	0	0
T61	7614	2	0	0
T72	732095	213	0	0
T74	8212	4	0	0
T76	5575	8	0	0
T77	245644	139	0	0
T82	997526	158	0	0