| | | | | | | |
dap |
85.53 |
98.68 |
93.42 |
|
66.00 |
94.57 |
75.00 |
i_dmi_cdc |
88.09 |
100.00 |
87.27 |
|
|
98.41 |
66.67 |
i_cdc_req |
82.95 |
100.00 |
81.82 |
|
|
100.00 |
50.00 |
u_prim_sync_reqack |
79.17 |
100.00 |
66.67 |
|
|
100.00 |
50.00 |
gen_rz_hs_protocol.ack_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rz_hs_protocol.req_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
i_cdc_resp |
83.04 |
100.00 |
85.71 |
|
|
96.43 |
50.00 |
u_prim_sync_reqack |
77.98 |
100.00 |
66.67 |
|
|
95.24 |
50.00 |
gen_rz_hs_protocol.ack_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_rz_hs_protocol.req_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_combined_rstn_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_rst_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
i_dmi_jtag_tap |
92.87 |
100.00 |
100.00 |
|
65.79 |
98.57 |
100.00 |
i_tck_inv |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_scan.i_dft_tck_mux |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
100.00 |
100.00 |
100.00 |
|
|
|
100.00 |
gen_alert_tx[0].u_prim_alert_sender |
83.33 |
|
|
83.33 |
|
|
|
i_tlul_adapter_reg |
93.27 |
99.00 |
80.90 |
93.33 |
|
93.10 |
100.00 |
gen_cmd_intg_check.u_cmd_intg_chk |
97.78 |
100.00 |
|
93.33 |
|
|
100.00 |
u_chk |
89.23 |
|
|
89.23 |
|
|
|
u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
u_err |
91.88 |
100.00 |
80.00 |
|
|
87.50 |
100.00 |
u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
rv_dm_regs_csr_assert |
100.00 |
|
|
|
|
|
100.00 |
tl_adapter_host_sba |
86.00 |
97.67 |
77.78 |
74.52 |
|
80.00 |
100.00 |
u_cmd_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
u_cmd_gen |
100.00 |
100.00 |
|
|
|
|
|
u_rsp_chk |
89.46 |
100.00 |
83.33 |
74.52 |
|
|
100.00 |
gen_rsp_data_intg_check.u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
u_chk |
58.85 |
|
|
58.85 |
|
|
|
tlul_assert_device_mem |
95.24 |
100.00 |
|
|
|
85.71 |
100.00 |
tlul_assert_device_regs |
95.00 |
100.00 |
|
|
|
85.71 |
99.30 |
tlul_assert_host_sba |
64.34 |
53.33 |
|
|
|
42.86 |
96.83 |
u_dm_top |
65.60 |
75.80 |
52.85 |
|
42.86 |
56.50 |
100.00 |
i_dm_csrs |
73.16 |
80.70 |
58.56 |
|
|
53.40 |
100.00 |
i_fifo |
93.06 |
100.00 |
77.78 |
|
|
94.44 |
100.00 |
gen_normal_fifo.u_fifo_cnt |
93.64 |
100.00 |
90.00 |
|
|
90.91 |
|
i_dm_mem |
76.23 |
79.70 |
53.12 |
|
100.00 |
72.09 |
|
gen_rom_snd_scratch.i_debug_rom |
94.44 |
100.00 |
100.00 |
|
|
83.33 |
|
i_dm_sba |
22.15 |
45.45 |
16.67 |
|
0.00 |
26.47 |
|
u_lc_en_sync_copies |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[4].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_pm_en_sync |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_flops.u_prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_clock_mux2 |
96.30 |
100.00 |
88.89 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
96.30 |
100.00 |
88.89 |
|
|
|
100.00 |
u_prim_flop_2sync_lc_rst_assert |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_flop_2sync_lc_rst_sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_lc_sync_lc_dft_en |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_flops.u_prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_lc_sync_lc_hw_debug_en |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_flops.u_prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_mubi32_sync_late_debug_enable |
100.00 |
100.00 |
|
|
|
|
100.00 |
subtree... |
|
|
|
|
|
|
|
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[4].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[5].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[6].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[7].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[4].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[5].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[6].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[7].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[4].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[5].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[6].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[2].gen_bits[7].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[4].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[5].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[6].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[3].gen_bits[7].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_flops.u_prim_flop_2sync |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_1 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_sync_2 |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_prim_rst_n_mux2 |
96.30 |
100.00 |
88.89 |
|
|
|
100.00 |
gen_generic.u_impl_generic |
96.30 |
100.00 |
88.89 |
|
|
|
100.00 |
u_reg_regs |
98.19 |
98.69 |
98.71 |
93.55 |
|
100.00 |
100.00 |
u_alert_test |
100.00 |
100.00 |
|
|
|
|
|
u_chk |
97.78 |
100.00 |
|
93.33 |
|
|
100.00 |
u_chk |
89.23 |
|
|
89.23 |
|
|
|
u_tlul_data_integ_dec |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_data_chk |
100.00 |
|
|
100.00 |
|
|
|
u_late_debug_enable |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
u_late_debug_enable_regwen |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
|
wr_en_data_arb |
100.00 |
100.00 |
100.00 |
|
|
|
|
u_prim_reg_we_check |
100.00 |
100.00 |
|
100.00 |
|
|
|
u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_prim_onehot_check |
100.00 |
|
|
100.00 |
|
|
|
u_reg_if |
98.67 |
97.14 |
97.53 |
|
|
100.00 |
100.00 |
u_err |
100.00 |
100.00 |
100.00 |
|
|
100.00 |
100.00 |
u_rsp_intg_gen |
83.33 |
66.67 |
|
|
|
|
100.00 |
u_rsp_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
u_tlul_lc_gate_rom |
82.58 |
93.70 |
67.86 |
|
85.71 |
78.12 |
87.50 |
gen_lc_gating_muxes[0].u_prim_blanker_d2h |
100.00 |
100.00 |
|
|
|
|
|
u_blank_and |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_lc_gating_muxes[0].u_prim_blanker_h2d |
100.00 |
100.00 |
|
|
|
|
|
u_blank_and |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_lc_gating_muxes[1].u_prim_blanker_d2h |
100.00 |
100.00 |
|
|
|
|
|
u_blank_and |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_lc_gating_muxes[1].u_prim_blanker_h2d |
100.00 |
100.00 |
|
|
|
|
|
u_blank_and |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_err_en_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_tlul_err_resp |
71.59 |
86.36 |
50.00 |
|
|
50.00 |
100.00 |
u_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|
u_tlul_lc_gate_sba |
59.17 |
84.25 |
39.29 |
|
28.57 |
56.25 |
87.50 |
gen_lc_gating_muxes[0].u_prim_blanker_d2h |
100.00 |
100.00 |
|
|
|
|
|
u_blank_and |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_lc_gating_muxes[0].u_prim_blanker_h2d |
100.00 |
100.00 |
|
|
|
|
|
u_blank_and |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_lc_gating_muxes[1].u_prim_blanker_d2h |
100.00 |
100.00 |
|
|
|
|
|
u_blank_and |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_lc_gating_muxes[1].u_prim_blanker_h2d |
100.00 |
100.00 |
|
|
|
|
|
u_blank_and |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_err_en_sync |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_buffs[0].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[0].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[0].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[1].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[2].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
gen_buffs[1].gen_bits[3].u_prim_buf |
100.00 |
100.00 |
|
|
|
|
|
u_secure_anchor_buf |
100.00 |
100.00 |
|
|
|
|
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
|
|
u_state_regs |
100.00 |
100.00 |
|
|
|
100.00 |
100.00 |
u_state_flop |
100.00 |
100.00 |
|
|
|
100.00 |
|
gen_generic.u_impl_generic |
100.00 |
100.00 |
|
|
|
100.00 |
|
u_tlul_err_resp |
71.59 |
86.36 |
50.00 |
|
|
50.00 |
100.00 |
u_intg_gen |
100.00 |
100.00 |
|
|
|
|
100.00 |
gen_data_intg.u_tlul_data_integ_enc |
100.00 |
100.00 |
|
|
|
|
|
u_data_gen |
100.00 |
100.00 |
|
|
|
|
|
gen_rsp_intg.u_rsp_gen |
100.00 |
100.00 |
|
|
|
|
|