Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.30 100.00 88.89 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9
11CoveredT9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10316325 10315641 0 0
selKnown1 11426464 11425780 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10316325 10315641 0 0
T1 338 336 0 0
T2 306 304 0 0
T3 364 362 0 0
T4 306 304 0 0
T5 3188 3186 0 0
T6 10 8 0 0
T7 12 10 0 0
T9 0 7 0 0
T10 2 0 0 0
T11 0 6 0 0
T12 2 0 0 0
T13 0 13 0 0
T16 310 308 0 0
T18 374 372 0 0
T19 306 304 0 0
T20 380 378 0 0
T21 368 366 0 0
T22 22 20 0 0
T23 0 20 0 0
T24 0 40 0 0
T34 2 0 0 0
T35 2 0 0 0
T45 2 0 0 0
T51 2 0 0 0
T52 2 0 0 0
T55 0 20 0 0
T56 0 20 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 11426464 11425780 0 0
T1 1329 1327 0 0
T2 1431 1429 0 0
T3 1875 1873 0 0
T4 1504 1502 0 0
T5 5346 5344 0 0
T6 10 8 0 0
T7 8 6 0 0
T9 0 8 0 0
T10 2 0 0 0
T11 0 6 0 0
T12 2 0 0 0
T13 0 6 0 0
T16 1619 1617 0 0
T18 2055 2053 0 0
T19 1883 1881 0 0
T20 2198 2196 0 0
T21 2941 2939 0 0
T22 22 20 0 0
T23 0 20 0 0
T24 0 40 0 0
T34 2 0 0 0
T35 2 0 0 0
T45 2 0 0 0
T51 2 0 0 0
T52 2 0 0 0
T55 0 20 0 0
T56 0 20 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9
11CoveredT9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 258405 258338 0 0
selKnown1 1368653 1368586 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 258405 258338 0 0
T1 169 168 0 0
T2 153 152 0 0
T3 182 181 0 0
T4 153 152 0 0
T5 1594 1593 0 0
T16 155 154 0 0
T18 187 186 0 0
T19 153 152 0 0
T20 190 189 0 0
T21 184 183 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1368653 1368586 0 0
T1 1160 1159 0 0
T2 1278 1277 0 0
T3 1693 1692 0 0
T4 1351 1350 0 0
T5 3752 3751 0 0
T16 1464 1463 0 0
T18 1868 1867 0 0
T19 1730 1729 0 0
T20 2008 2007 0 0
T21 2757 2756 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9
11CoveredT9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 144 77 0 0
selKnown1 144 77 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 144 77 0 0
T6 5 4 0 0
T7 5 4 0 0
T9 0 3 0 0
T10 1 0 0 0
T11 0 3 0 0
T12 1 0 0 0
T13 0 3 0 0
T22 11 10 0 0
T23 0 10 0 0
T24 0 20 0 0
T34 1 0 0 0
T35 1 0 0 0
T45 1 0 0 0
T51 1 0 0 0
T52 1 0 0 0
T55 0 10 0 0
T56 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 144 77 0 0
T6 5 4 0 0
T7 4 3 0 0
T9 0 4 0 0
T10 1 0 0 0
T11 0 3 0 0
T12 1 0 0 0
T13 0 3 0 0
T22 11 10 0 0
T23 0 10 0 0
T24 0 20 0 0
T34 1 0 0 0
T35 1 0 0 0
T45 1 0 0 0
T51 1 0 0 0
T52 1 0 0 0
T55 0 10 0 0
T56 0 10 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9
11CoveredT9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 10056183 10055908 0 0
selKnown1 10056183 10055908 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 10056183 10055908 0 0
T1 169 168 0 0
T2 153 152 0 0
T3 182 181 0 0
T4 153 152 0 0
T5 1594 1593 0 0
T16 155 154 0 0
T18 187 186 0 0
T19 153 152 0 0
T20 190 189 0 0
T21 184 183 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 10056183 10055908 0 0
T1 169 168 0 0
T2 153 152 0 0
T3 182 181 0 0
T4 153 152 0 0
T5 1594 1593 0 0
T16 155 154 0 0
T18 187 186 0 0
T19 153 152 0 0
T20 190 189 0 0
T21 184 183 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT9

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9
11CoveredT9

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT9
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1593 1318 0 0
selKnown1 1484 1209 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1593 1318 0 0
T6 5 4 0 0
T7 7 6 0 0
T9 0 4 0 0
T10 1 0 0 0
T11 0 3 0 0
T12 1 0 0 0
T13 0 10 0 0
T22 11 10 0 0
T23 0 10 0 0
T24 0 20 0 0
T34 1 0 0 0
T35 1 0 0 0
T45 1 0 0 0
T51 1 0 0 0
T52 1 0 0 0
T55 0 10 0 0
T56 0 10 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1484 1209 0 0
T6 5 4 0 0
T7 4 3 0 0
T9 0 4 0 0
T10 1 0 0 0
T11 0 3 0 0
T12 1 0 0 0
T13 0 3 0 0
T22 11 10 0 0
T23 0 10 0 0
T24 0 20 0 0
T34 1 0 0 0
T35 1 0 0 0
T45 1 0 0 0
T51 1 0 0 0
T52 1 0 0 0
T55 0 10 0 0
T56 0 10 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%