SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync_lc_hw_debug_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_prim_lc_sync_lc_dft_en | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_en_sync_copies | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
85.64 | 100.00 | 55.32 | 85.38 | 100.00 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
47.72 | 72.55 | 33.33 | 28.57 | 54.17 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
78.58 | 96.08 | 77.78 | 85.71 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 402 | 402 | 0 | 0 |
OutputsKnown_A | 8211918 | 8153736 | 0 | 0 |
gen_flops.OutputDelay_A | 4105959 | 4075572 | 0 | 603 |
gen_no_flops.OutputDelay_A | 4105959 | 4076868 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 402 | 402 | 0 | 0 |
T1 | 6 | 6 | 0 | 0 |
T2 | 6 | 6 | 0 | 0 |
T3 | 6 | 6 | 0 | 0 |
T4 | 6 | 6 | 0 | 0 |
T5 | 6 | 6 | 0 | 0 |
T16 | 6 | 6 | 0 | 0 |
T18 | 6 | 6 | 0 | 0 |
T19 | 6 | 6 | 0 | 0 |
T20 | 6 | 6 | 0 | 0 |
T21 | 6 | 6 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 8211918 | 8153736 | 0 | 0 |
T1 | 6960 | 6498 | 0 | 0 |
T2 | 7668 | 7242 | 0 | 0 |
T3 | 10158 | 9828 | 0 | 0 |
T4 | 8106 | 7800 | 0 | 0 |
T5 | 22512 | 22002 | 0 | 0 |
T16 | 8784 | 8364 | 0 | 0 |
T18 | 11208 | 10734 | 0 | 0 |
T19 | 10380 | 10026 | 0 | 0 |
T20 | 12048 | 11556 | 0 | 0 |
T21 | 16542 | 16068 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 4105959 | 4075572 | 0 | 603 |
T1 | 3480 | 3240 | 0 | 9 |
T2 | 3834 | 3612 | 0 | 9 |
T3 | 5079 | 4905 | 0 | 9 |
T4 | 4053 | 3891 | 0 | 9 |
T5 | 11256 | 10992 | 0 | 9 |
T16 | 4392 | 4173 | 0 | 9 |
T18 | 5604 | 5358 | 0 | 9 |
T19 | 5190 | 5004 | 0 | 9 |
T20 | 6024 | 5769 | 0 | 9 |
T21 | 8271 | 8025 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 4105959 | 4076868 | 0 | 0 |
T1 | 3480 | 3249 | 0 | 0 |
T2 | 3834 | 3621 | 0 | 0 |
T3 | 5079 | 4914 | 0 | 0 |
T4 | 4053 | 3900 | 0 | 0 |
T5 | 11256 | 11001 | 0 | 0 |
T16 | 4392 | 4182 | 0 | 0 |
T18 | 5604 | 5367 | 0 | 0 |
T19 | 5190 | 5013 | 0 | 0 |
T20 | 6024 | 5778 | 0 | 0 |
T21 | 8271 | 8034 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 67 | 67 | 0 | 0 |
OutputsKnown_A | 1368653 | 1358956 | 0 | 0 |
gen_flops.OutputDelay_A | 1368653 | 1358524 | 0 | 201 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 67 | 67 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358956 | 0 | 0 |
T1 | 1160 | 1083 | 0 | 0 |
T2 | 1278 | 1207 | 0 | 0 |
T3 | 1693 | 1638 | 0 | 0 |
T4 | 1351 | 1300 | 0 | 0 |
T5 | 3752 | 3667 | 0 | 0 |
T16 | 1464 | 1394 | 0 | 0 |
T18 | 1868 | 1789 | 0 | 0 |
T19 | 1730 | 1671 | 0 | 0 |
T20 | 2008 | 1926 | 0 | 0 |
T21 | 2757 | 2678 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358524 | 0 | 201 |
T1 | 1160 | 1080 | 0 | 3 |
T2 | 1278 | 1204 | 0 | 3 |
T3 | 1693 | 1635 | 0 | 3 |
T4 | 1351 | 1297 | 0 | 3 |
T5 | 3752 | 3664 | 0 | 3 |
T16 | 1464 | 1391 | 0 | 3 |
T18 | 1868 | 1786 | 0 | 3 |
T19 | 1730 | 1668 | 0 | 3 |
T20 | 2008 | 1923 | 0 | 3 |
T21 | 2757 | 2675 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 67 | 67 | 0 | 0 |
OutputsKnown_A | 1368653 | 1358956 | 0 | 0 |
gen_flops.OutputDelay_A | 1368653 | 1358524 | 0 | 201 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 67 | 67 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358956 | 0 | 0 |
T1 | 1160 | 1083 | 0 | 0 |
T2 | 1278 | 1207 | 0 | 0 |
T3 | 1693 | 1638 | 0 | 0 |
T4 | 1351 | 1300 | 0 | 0 |
T5 | 3752 | 3667 | 0 | 0 |
T16 | 1464 | 1394 | 0 | 0 |
T18 | 1868 | 1789 | 0 | 0 |
T19 | 1730 | 1671 | 0 | 0 |
T20 | 2008 | 1926 | 0 | 0 |
T21 | 2757 | 2678 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358524 | 0 | 201 |
T1 | 1160 | 1080 | 0 | 3 |
T2 | 1278 | 1204 | 0 | 3 |
T3 | 1693 | 1635 | 0 | 3 |
T4 | 1351 | 1297 | 0 | 3 |
T5 | 3752 | 3664 | 0 | 3 |
T16 | 1464 | 1391 | 0 | 3 |
T18 | 1868 | 1786 | 0 | 3 |
T19 | 1730 | 1668 | 0 | 3 |
T20 | 2008 | 1923 | 0 | 3 |
T21 | 2757 | 2675 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 67 | 67 | 0 | 0 |
OutputsKnown_A | 1368653 | 1358956 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1368653 | 1358956 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 67 | 67 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358956 | 0 | 0 |
T1 | 1160 | 1083 | 0 | 0 |
T2 | 1278 | 1207 | 0 | 0 |
T3 | 1693 | 1638 | 0 | 0 |
T4 | 1351 | 1300 | 0 | 0 |
T5 | 3752 | 3667 | 0 | 0 |
T16 | 1464 | 1394 | 0 | 0 |
T18 | 1868 | 1789 | 0 | 0 |
T19 | 1730 | 1671 | 0 | 0 |
T20 | 2008 | 1926 | 0 | 0 |
T21 | 2757 | 2678 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358956 | 0 | 0 |
T1 | 1160 | 1083 | 0 | 0 |
T2 | 1278 | 1207 | 0 | 0 |
T3 | 1693 | 1638 | 0 | 0 |
T4 | 1351 | 1300 | 0 | 0 |
T5 | 3752 | 3667 | 0 | 0 |
T16 | 1464 | 1394 | 0 | 0 |
T18 | 1868 | 1789 | 0 | 0 |
T19 | 1730 | 1671 | 0 | 0 |
T20 | 2008 | 1926 | 0 | 0 |
T21 | 2757 | 2678 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 67 | 67 | 0 | 0 |
OutputsKnown_A | 1368653 | 1358956 | 0 | 0 |
gen_flops.OutputDelay_A | 1368653 | 1358524 | 0 | 201 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 67 | 67 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358956 | 0 | 0 |
T1 | 1160 | 1083 | 0 | 0 |
T2 | 1278 | 1207 | 0 | 0 |
T3 | 1693 | 1638 | 0 | 0 |
T4 | 1351 | 1300 | 0 | 0 |
T5 | 3752 | 3667 | 0 | 0 |
T16 | 1464 | 1394 | 0 | 0 |
T18 | 1868 | 1789 | 0 | 0 |
T19 | 1730 | 1671 | 0 | 0 |
T20 | 2008 | 1926 | 0 | 0 |
T21 | 2757 | 2678 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358524 | 0 | 201 |
T1 | 1160 | 1080 | 0 | 3 |
T2 | 1278 | 1204 | 0 | 3 |
T3 | 1693 | 1635 | 0 | 3 |
T4 | 1351 | 1297 | 0 | 3 |
T5 | 3752 | 3664 | 0 | 3 |
T16 | 1464 | 1391 | 0 | 3 |
T18 | 1868 | 1786 | 0 | 3 |
T19 | 1730 | 1668 | 0 | 3 |
T20 | 2008 | 1923 | 0 | 3 |
T21 | 2757 | 2675 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 67 | 67 | 0 | 0 |
OutputsKnown_A | 1368653 | 1358956 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1368653 | 1358956 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 67 | 67 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358956 | 0 | 0 |
T1 | 1160 | 1083 | 0 | 0 |
T2 | 1278 | 1207 | 0 | 0 |
T3 | 1693 | 1638 | 0 | 0 |
T4 | 1351 | 1300 | 0 | 0 |
T5 | 3752 | 3667 | 0 | 0 |
T16 | 1464 | 1394 | 0 | 0 |
T18 | 1868 | 1789 | 0 | 0 |
T19 | 1730 | 1671 | 0 | 0 |
T20 | 2008 | 1926 | 0 | 0 |
T21 | 2757 | 2678 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358956 | 0 | 0 |
T1 | 1160 | 1083 | 0 | 0 |
T2 | 1278 | 1207 | 0 | 0 |
T3 | 1693 | 1638 | 0 | 0 |
T4 | 1351 | 1300 | 0 | 0 |
T5 | 3752 | 3667 | 0 | 0 |
T16 | 1464 | 1394 | 0 | 0 |
T18 | 1868 | 1789 | 0 | 0 |
T19 | 1730 | 1671 | 0 | 0 |
T20 | 2008 | 1926 | 0 | 0 |
T21 | 2757 | 2678 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 67 | 67 | 0 | 0 |
OutputsKnown_A | 1368653 | 1358956 | 0 | 0 |
gen_no_flops.OutputDelay_A | 1368653 | 1358956 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 67 | 67 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
T18 | 1 | 1 | 0 | 0 |
T19 | 1 | 1 | 0 | 0 |
T20 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358956 | 0 | 0 |
T1 | 1160 | 1083 | 0 | 0 |
T2 | 1278 | 1207 | 0 | 0 |
T3 | 1693 | 1638 | 0 | 0 |
T4 | 1351 | 1300 | 0 | 0 |
T5 | 3752 | 3667 | 0 | 0 |
T16 | 1464 | 1394 | 0 | 0 |
T18 | 1868 | 1789 | 0 | 0 |
T19 | 1730 | 1671 | 0 | 0 |
T20 | 2008 | 1926 | 0 | 0 |
T21 | 2757 | 2678 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 1368653 | 1358956 | 0 | 0 |
T1 | 1160 | 1083 | 0 | 0 |
T2 | 1278 | 1207 | 0 | 0 |
T3 | 1693 | 1638 | 0 | 0 |
T4 | 1351 | 1300 | 0 | 0 |
T5 | 3752 | 3667 | 0 | 0 |
T16 | 1464 | 1394 | 0 | 0 |
T18 | 1868 | 1789 | 0 | 0 |
T19 | 1730 | 1671 | 0 | 0 |
T20 | 2008 | 1926 | 0 | 0 |
T21 | 2757 | 2678 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |