Toggle Coverage for Module :
prim_secded_inv_64_57_dec
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T2,*T4,*T16 |
Yes |
T2,T4,T16 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T2,T4,T16 |
Yes |
T2,T4,T16 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T2,T16,T18 |
Yes |
T2,T16,T18 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T1,T2,T4 |
Yes |
T2,T4,T16 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.tl_adapter_host_sba.u_rsp_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
2 |
50.00 |
Total Bits |
260 |
153 |
58.85 |
Total Bits 0->1 |
130 |
77 |
59.23 |
Total Bits 1->0 |
130 |
76 |
58.46 |
| | | |
Ports |
4 |
2 |
50.00 |
Port Bits |
260 |
153 |
58.85 |
Port Bits 0->1 |
130 |
77 |
59.23 |
Port Bits 1->0 |
130 |
76 |
58.46 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[3:0] |
Yes |
Yes |
*T18,*T21,*T58 |
Yes |
T50,T60,T36 |
INPUT |
data_i[56:4] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T50,T60,T36 |
Yes |
T2,T12,T48 |
INPUT |
data_o[21:0] |
Yes |
Yes |
*T18,*T21,*T58 |
Yes |
T50,T60,T36 |
OUTPUT |
data_o[22] |
No |
No |
|
Yes |
T61 |
OUTPUT |
data_o[56:23] |
Yes |
Yes |
T50,T60,T62 |
Yes |
T44,T50,T60 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T50,T60,T37 |
Yes |
T18,T45,T51 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T50,T60,T37 |
Yes |
T2,T18,T21 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.u_reg_regs.u_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T2,*T4,*T16 |
Yes |
T2,T4,T16 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T2,T4,T16 |
Yes |
T2,T4,T16 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T2,T16,T18 |
Yes |
T2,T16,T18 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T2,T4,T16 |
Yes |
T2,T4,T16 |
OUTPUT |
*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.i_tlul_adapter_reg.gen_cmd_intg_check.u_cmd_intg_chk.u_chk
| Total | Covered | Percent |
Totals |
4 |
3 |
75.00 |
Total Bits |
260 |
232 |
89.23 |
Total Bits 0->1 |
130 |
116 |
89.23 |
Total Bits 1->0 |
130 |
116 |
89.23 |
| | | |
Ports |
4 |
3 |
75.00 |
Port Bits |
260 |
232 |
89.23 |
Port Bits 0->1 |
130 |
116 |
89.23 |
Port Bits 1->0 |
130 |
116 |
89.23 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
data_i[42:0] |
Yes |
Yes |
*T5,*T6,*T7 |
Yes |
T16,T5,T20 |
INPUT |
data_i[56:43] |
No |
No |
|
No |
|
INPUT |
data_i[63:57] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T34 |
INPUT |
data_o[56:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T16,T5,T20 |
OUTPUT |
syndrome_o[6:0] |
Yes |
Yes |
T5,T7,T14 |
Yes |
T16,T5,T33 |
OUTPUT |
err_o[1:0] |
Yes |
Yes |
T1,T16,T5 |
Yes |
T5,T6,T7 |
OUTPUT |
*Tests covering at least one bit in the range