RV_DM Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.750s 929.411us 1 2 50.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.850s 217.009us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.890s 67.247us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 17.320s 5.658ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 0.870s 77.676us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 5.740s 1.787ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 6.110s 1.681ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.514m 30.492ms 5 5 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 1.365m 50.000ms 4 5 80.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 0.690s 31.759us 0 2 0.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 0.740s 67.366us 0 2 0.00
V1 cmderr_exception rv_dm_cmderr_exception 0.740s 28.530us 0 2 0.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 0.690s 25.683us 0 2 0.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.670s 21.024us 0 2 0.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 0.730s 35.721us 0 2 0.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.720s 19.741us 0 2 0.00
V1 halt_resume rv_dm_halt_resume_whereto 0.710s 11.247us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 0.700s 27.942us 0 2 0.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.680s 65.215us 0 2 0.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.920s 116.052us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 0.740s 28.530us 0 2 0.00
V1 rom_read_access rv_dm_rom_read_access 0.880s 39.546us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.410s 122.798us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.490s 171.344us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.257m 9.633ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.251m 16.541ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 13.110s 5.892ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.251m 16.541ms 5 5 100.00
rv_dm_csr_rw 2.490s 171.344us 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.790s 29.705us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.710s 45.890us 5 5 100.00
V1 TOTAL 139 161 86.34
V2 idcode rv_dm_smoke 1.750s 929.411us 1 2 50.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 0.700s 9.692us 0 2 0.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.790s 46.421us 2 2 100.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0.830s 117.060us 0 2 0.00
V2 sba rv_dm_sba_tl_access 1.000s 115.356us 0 20 0.00
rv_dm_delayed_resp_sba_tl_access 0.800s 39.598us 0 20 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 0.780s 30.789us 0 20 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 0.850s 59.919us 0 20 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.670s 45.739us 0 2 0.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 0.790s 38.983us 0 2 0.00
V2 hart_unavail rv_dm_hart_unavail 0.700s 19.791us 0 5 0.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 0.710s 24.585us 0 1 0.00
rv_dm_tap_fsm_rand_reset 39.660s 20.781ms 17 40 42.50
V2 stress_all rv_dm_stress_all 22.140s 7.321ms 5 50 10.00
V2 alert_test rv_dm_alert_test 0.810s 29.809us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.440s 259.137us 17 20 85.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.440s 259.137us 17 20 85.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.251m 16.541ms 5 5 100.00
rv_dm_csr_hw_reset 2.410s 122.798us 5 5 100.00
rv_dm_csr_rw 2.490s 171.344us 20 20 100.00
rv_dm_same_csr_outstanding 7.880s 4.001ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.251m 16.541ms 5 5 100.00
rv_dm_csr_hw_reset 2.410s 122.798us 5 5 100.00
rv_dm_csr_rw 2.490s 171.344us 20 20 100.00
rv_dm_same_csr_outstanding 7.880s 4.001ms 20 20 100.00
V2 TOTAL 111 276 40.22
V2S tl_intg_err rv_dm_sec_cm 1.630s 226.902us 5 5 100.00
rv_dm_tl_intg_err 20.570s 1.897ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 27.000s 2.016ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 275 512 53.71

Testplan Progress

Items Total Written Passing Progress
V1 28 28 16 57.14
V2 18 16 3 16.67
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
74.74 90.63 76.24 86.29 60.26 77.17 98.20 34.39

Failure Buckets

Past Results