8cb25a6867| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 4.140s | 3.567ms | 2 | 2 | 100.00 |
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 2.490s | 1.319ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 3.760s | 1.209ms | 20 | 20 | 100.00 |
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 2.069m | 48.348ms | 5 | 5 | 100.00 |
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 2.610s | 2.374ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 22.870s | 8.584ms | 5 | 5 | 100.00 |
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 46.710s | 15.793ms | 20 | 20 | 100.00 |
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 4.350m | 92.403ms | 3 | 5 | 60.00 |
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 1.721m | 36.761ms | 2 | 5 | 40.00 |
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 21.890s | 7.021ms | 2 | 2 | 100.00 |
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 6.520s | 9.474ms | 2 | 2 | 100.00 |
| V1 | cmderr_exception | rv_dm_cmderr_exception | 1.290s | 913.823us | 2 | 2 | 100.00 |
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 15.010s | 5.573ms | 2 | 2 | 100.00 |
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 1.240s | 298.030us | 2 | 2 | 100.00 |
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 3.080s | 1.327ms | 2 | 2 | 100.00 |
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0.820s | 114.112us | 2 | 2 | 100.00 |
| V1 | halt_resume | rv_dm_halt_resume_whereto | 4.220s | 2.645ms | 2 | 2 | 100.00 |
| V1 | progbuf_busy | rv_dm_progbuf_busy | 1.820s | 1.171ms | 2 | 2 | 100.00 |
| V1 | abstractcmd_status | rv_dm_abstractcmd_status | 1.800s | 426.923us | 2 | 2 | 100.00 |
| V1 | progbuf_read_write_execute | rv_dm_progbuf_read_write_execute | 3.390s | 924.133us | 2 | 2 | 100.00 |
| V1 | progbuf_exception | rv_dm_cmderr_exception | 1.290s | 913.823us | 2 | 2 | 100.00 |
| V1 | rom_read_access | rv_dm_rom_read_access | 0.840s | 148.299us | 2 | 2 | 100.00 |
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 2.640s | 160.554us | 5 | 5 | 100.00 |
| V1 | csr_rw | rv_dm_csr_rw | 2.490s | 272.113us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 1.257m | 14.939ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | rv_dm_csr_aliasing | 1.123m | 2.322ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 10.320s | 3.433ms | 17 | 20 | 85.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 1.123m | 2.322ms | 5 | 5 | 100.00 |
| rv_dm_csr_rw | 2.490s | 272.113us | 20 | 20 | 100.00 | ||
| V1 | mem_walk | rv_dm_mem_walk | 0.930s | 193.650us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0.870s | 106.142us | 5 | 5 | 100.00 |
| V1 | TOTAL | 153 | 161 | 95.03 | |||
| V2 | idcode | rv_dm_smoke | 4.140s | 3.567ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 15.000s | 10.763ms | 2 | 2 | 100.00 |
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 1.350s | 247.231us | 2 | 2 | 100.00 |
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 1.710s | 1.443ms | 2 | 2 | 100.00 |
| V2 | sba | rv_dm_sba_tl_access | 2.253m | 50.000ms | 15 | 20 | 75.00 |
| rv_dm_delayed_resp_sba_tl_access | 2.267m | 50.000ms | 17 | 20 | 85.00 | ||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 2.115m | 50.000ms | 12 | 20 | 60.00 |
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 2.588m | 50.000ms | 2 | 20 | 10.00 |
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 2.880s | 856.954us | 2 | 2 | 100.00 |
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 8.150s | 2.734ms | 2 | 2 | 100.00 |
| V2 | hart_unavail | rv_dm_hart_unavail | 2.800s | 825.839us | 5 | 5 | 100.00 |
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 22.240s | 7.788ms | 1 | 1 | 100.00 |
| rv_dm_tap_fsm_rand_reset | 1.261m | 50.000ms | 1 | 40 | 2.50 | ||
| V2 | stress_all | rv_dm_stress_all | 2.612h | 10.000s | 17 | 50 | 34.00 |
| V2 | alert_test | rv_dm_alert_test | 1.120s | 157.711us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 6.490s | 1.162ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 6.490s | 1.162ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 1.123m | 2.322ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.640s | 160.554us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.490s | 272.113us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 10.060s | 6.284ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 1.123m | 2.322ms | 5 | 5 | 100.00 |
| rv_dm_csr_hw_reset | 2.640s | 160.554us | 5 | 5 | 100.00 | ||
| rv_dm_csr_rw | 2.490s | 272.113us | 20 | 20 | 100.00 | ||
| rv_dm_same_csr_outstanding | 10.060s | 6.284ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 170 | 276 | 61.59 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 5.150s | 1.502ms | 5 | 5 | 100.00 |
| rv_dm_tl_intg_err | 25.960s | 4.835ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_lc_dft_en_intersig_mubi | sec_cm_lc_dft_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 9.739m | 75.697ms | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 348 | 512 | 67.97 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 28 | 28 | 25 | 89.29 |
| V2 | 18 | 16 | 10 | 55.56 |
| V2S | 10 | 2 | 2 | 20.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 78.09 | 94.66 | 81.18 | 86.65 | 70.51 | 84.50 | 98.52 | 30.59 |
UVM_ERROR (cip_base_vseq.sv:829) [rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 49 failures:
0.rv_dm_tap_fsm_rand_reset.102472845861973786794448461584929460065743547706563897703579429316772189751895
Line 270, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 9297204746 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9297204746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_tap_fsm_rand_reset.50343989070532918866279182003237321417876589425009385593807023355389468815135
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 1548338857 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1548338857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
1.rv_dm_csr_mem_rw_with_rand_reset.110898526850102386106481633094442708591378856677055957752171439157562899974045
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 291026268 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 291026268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_dm_csr_mem_rw_with_rand_reset.100073526558347101915563161314176781933485867513018755786552880899765292729586
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 217612288 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 217612288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
23.rv_dm_stress_all_with_rand_reset.46835144517175868119445777142299177628202447247227113192063801592324063040307
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/23.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 313373996 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 313373996 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.rv_dm_stress_all_with_rand_reset.83386821314466107066304902571801098401084204269810687371587737926950146361940
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/26.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 247381873 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 247381873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 42 failures:
0.rv_dm_jtag_dmi_csr_aliasing.56165679015223358947609081276269206055109238563959213841647254859565962330007
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dmi_csr_aliasing/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_jtag_dmi_csr_aliasing.59617004689858789307977193821673633488444169571810017388185076418283773896648
Line 252, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_jtag_dmi_csr_aliasing/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rv_dm_delayed_resp_sba_tl_access.109310814462668680510799682892103098431728650683620916525090576469680585901335
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_delayed_resp_sba_tl_access.19593592468228697490523805235256613324535612419563813156511088245245151394846
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_delayed_resp_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
0.rv_dm_bad_sba_tl_access.63872346190894524599816314275558221427956230836460345698069510548196234316349
Line 416, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.rv_dm_bad_sba_tl_access.16391705605293651246475588915424661309362404973380706578099984582366389078168
Line 350, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_bad_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
0.rv_dm_autoincr_sba_tl_access.32442799309864117417791898113882816556842787016426241250852462059380787806364
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.rv_dm_autoincr_sba_tl_access.78759151531274142933974390593039157921368195518705146744086897453078676909081
Line 278, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
1.rv_dm_sba_tl_access.5115431724519283627547608114541652649754642719670258839313358222294466193748
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.rv_dm_sba_tl_access.101809036474114021955594471850434952660702513981145938867397553433803879577203
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_sba_tl_access/latest/run.log
UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:98) [scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (* [*] vs * [*]) has 8 failures:
2.rv_dm_stress_all.96874398465462967018057530807761922134934854133625604073008257993547399398795
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 6880058920 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (274877906948 [0x4000000004] vs 4209 [0x1071])
UVM_INFO @ 6880058920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.rv_dm_stress_all.6174242091332446273431603334988250153906329463747622391342233126419820493589
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/20.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 10844284021 ps: (rv_dm_scoreboard.sv:98) [uvm_test_top.env.scoreboard] Check failed item.dout & mask == selected_dtm_csr.get_mirrored_value() & mask (274877906948 [0x4000000004] vs 4209 [0x1071])
UVM_INFO @ 10844284021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (rv_dm_scoreboard.sv:366) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: rv_dm_mem_reg_block.dataaddr_* has 7 failures:
1.rv_dm_stress_all_with_rand_reset.12400370799228362808464757464759271760161634114200258816981155484166782744239
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 505797740 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (2450588752 [0x92110450] vs 2450602454 [0x921139d6]) reg name: rv_dm_mem_reg_block.dataaddr_1
UVM_INFO @ 505797740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.rv_dm_stress_all_with_rand_reset.45545890285331815621965866970817195257027174033481913933120570310753940262235
Line 256, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/9.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1485790338 ps: (rv_dm_scoreboard.sv:366) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1484011778 [0x58743902] vs 1484035359 [0x5874951f]) reg name: rv_dm_mem_reg_block.dataaddr_0
UVM_INFO @ 1485790338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
Job rv_dm-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 6 failures:
10.rv_dm_stress_all.20641494716515543807654630418533021777045608761891244752229799516143464371970
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all/latest/run.log
Job ID: smart:bd1d9051-7ed9-484d-afe5-2d9bccad28de
13.rv_dm_stress_all.45203212429099617982850086658858872091030588092673228260627371290939723467421
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all/latest/run.log
Job ID: smart:41423cc6-5ee4-48ed-8d04-635db4f52b46
... and 4 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:193) [rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 5 failures:
4.rv_dm_stress_all_with_rand_reset.88733270122121792366733790580592232701432339988750549816177548047742156737109
Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7325773964 ps: (rv_dm_base_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 7325773964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.rv_dm_stress_all_with_rand_reset.95948617176704258801973315429582852147652681148337593488411183939497408014180
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1664983196 ps: (rv_dm_base_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 3 [0x3])
UVM_INFO @ 1664983196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
8.rv_dm_stress_all.34399796602509608359178720151505123940548875008067689822044399955692592503830
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 29512660512 ps: (rv_dm_base_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (2 [0x2] vs 1 [0x1])
UVM_INFO @ 29512660512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 4 failures:
0.rv_dm_stress_all_with_rand_reset.53706910527940250588580359195953473323992891100436077742273320138759992778598
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1183154490 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (2 [0x2] vs 157 [0x9d])
UVM_INFO @ 1183154490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.rv_dm_stress_all_with_rand_reset.4203963396053998281691774053752790320771427902731910561441584599843767646881
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/14.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 827915446 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (19 [0x13] vs 14 [0xe])
UVM_INFO @ 827915446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
3.rv_dm_stress_all.13102817380462236183309905044642225940292002975814624381854523440251631821584
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 9747831712 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (19 [0x13] vs 2958143569 [0xb051b051])
UVM_INFO @ 9747831712 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:83) [scoreboard] Check failed rwdata == * (* [*] vs * [*]) has 4 failures:
1.rv_dm_stress_all.103813646832657913343981673794506233724569878784312450767223781728054268806489
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 628066414 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 628066414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all.27759491689999958491120075739850579184111057420941584538833733767567665001718
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 1497805874 ps: (rv_dm_scoreboard.sv:83) [uvm_test_top.env.scoreboard] Check failed rwdata == 0 (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1497805874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable has 4 failures:
11.rv_dm_stress_all_with_rand_reset.55503337383851506126489855560098169783721012329837369223626953298990160194064
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1179107283 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 1179107283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.rv_dm_stress_all_with_rand_reset.82462875576254814278723274551589919708385433136739699505651281642799673069129
Line 498, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/13.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 75697043140 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable
UVM_INFO @ 75697043140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata* (* [*] vs * [*]) has 4 failures:
24.rv_dm_stress_all_with_rand_reset.96172739759474498843163803526650717480507506289653007891689185003525874265432
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/24.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1641584784 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (4 [0x4] vs 231 [0xe7])
UVM_INFO @ 1641584784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.rv_dm_stress_all_with_rand_reset.71652284186485109536028669525266945849757908789176655127423793913459882911152
Line 418, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/32.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 66292146890 ps: (rv_dm_jtag_dtm_hard_reset_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dtm_hard_reset_vseq] Check failed wdata == rdata1 (13 [0xd] vs 0 [0x0])
UVM_INFO @ 66292146890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [*] vs * [*]) has 3 failures:
Test rv_dm_stress_all has 1 failures.
11.rv_dm_stress_all.68141934824326469126523433440967541687429053304569695787389236756656414787527
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/11.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 22233358641 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 3223332399 [0xc020262f])
UVM_INFO @ 22233358641 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 2 failures.
42.rv_dm_stress_all_with_rand_reset.33092865567530646149361753577525629576515603387300639462430924593109277437239
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/42.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1402733343 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (1485744515 [0x588ea983] vs 1485732227 [0x588e7983])
UVM_INFO @ 1402733343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
48.rv_dm_stress_all_with_rand_reset.101770601197119082279291442336774447151671730873219127800491891964617038634037
Line 264, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/48.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4488469542 ps: (rv_dm_jtag_dmi_debug_disabled_vseq.sv:25) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (2958143569 [0xb051b051] vs 4277836300 [0xfefa9a0c])
UVM_INFO @ 4488469542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:41) [rv_dm_mem_tl_access_resuming_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (* [*] vs * [*]) has 3 failures:
22.rv_dm_stress_all_with_rand_reset.47475158669687536898815192565630389176597947166912784300722844642855235445363
Line 261, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/22.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1487823011 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1487823011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
31.rv_dm_stress_all_with_rand_reset.89544821629867750469711094397933173190199174775496523374630600246948716996533
Line 266, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/31.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1382730298 ps: (rv_dm_mem_tl_access_resuming_vseq.sv:41) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_resuming_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyrunning, rdata) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 1382730298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (rv_dm_base_vseq.sv:193) [rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (* [*] vs * [*]) has 2 failures:
2.rv_dm_stress_all_with_rand_reset.95299541586144915533419263596080456595120225140654729390713863938768765915900
Line 254, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 148460264 ps: (rv_dm_base_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 148460264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.rv_dm_stress_all_with_rand_reset.40333834032432887674637879776112981614402165069757009973794694409402560013574
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/7.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2893227509 ps: (rv_dm_base_vseq.sv:193) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_busy_vseq] Check failed cmderr == get_field_val(jtag_dmi_ral.abstractcs.cmderr,rdata) (1 [0x1] vs 3 [0x3])
UVM_INFO @ 2893227509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_dm_scoreboard.sv:322) scoreboard [scoreboard] Unknown regs CSR: late_debug_enable_regwen has 2 failures:
3.rv_dm_stress_all_with_rand_reset.4972040109864254812711495320937564129910955678105089364465502930127791634102
Line 257, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/3.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 1967072853 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 1967072853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.rv_dm_stress_all_with_rand_reset.102678998060140021484266922272671575345602028414676483816444142244927917948177
Line 312, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/43.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 9021806507 ps: (rv_dm_scoreboard.sv:322) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Unknown regs CSR: late_debug_enable_regwen
UVM_INFO @ 9021806507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=*) has 2 failures:
Test rv_dm_stress_all has 1 failures.
4.rv_dm_stress_all.52066453150581314324275940508434604067235849068733079144288522088270986616360
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 2866969916 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xd2071100)
UVM_INFO @ 2866969916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test rv_dm_stress_all_with_rand_reset has 1 failures.
30.rv_dm_stress_all_with_rand_reset.9277831688559803353227516437095250880228474417983878632868165659021381456680
Line 269, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/30.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 7911710606 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.halted (addr=0xc36a9100)
UVM_INFO @ 7911710606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_sba_tl_access_vseq_lib.sv:120) [rv_dm_sba_tl_access_vseq] Check failed (!req.timed_out) has 2 failures:
5.rv_dm_sba_tl_access.114274496743943911037840805811921080201769510447436590255399786385503592265606
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/5.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 978233370 ps: (rv_dm_sba_tl_access_vseq_lib.sv:120) [uvm_test_top.env.virtual_sequencer.rv_dm_sba_tl_access_vseq] Check failed (!req.timed_out)
UVM_INFO @ 978233370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.rv_dm_sba_tl_access.6047322988304410570707070322758184162446609752022940147181610141353192619976
Line 262, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_sba_tl_access/latest/run.log
UVM_ERROR @ 159652942 ps: (rv_dm_sba_tl_access_vseq_lib.sv:120) [uvm_test_top.env.virtual_sequencer.rv_dm_sba_tl_access_vseq] Check failed (!req.timed_out)
UVM_INFO @ 159652942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.dataaddr_* (addr=*) has 2 failures:
6.rv_dm_stress_all.63104242486967721871326583675377475355986374016367392846493107767263835164036
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 13357507397 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.dataaddr_0 (addr=0x10c08380)
UVM_INFO @ 13357507397 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.rv_dm_stress_all.41764667151335585672762295794689078713119214851983270661803450819322920875100
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/39.rv_dm_stress_all/latest/run.log
UVM_FATAL @ 20443571961 ps: (csr_utils_pkg.sv:220) [csr_utils::csr_wr] Timeout waiting to csr_wr rv_dm_mem_reg_block.dataaddr_0 (addr=0x128f2380)
UVM_INFO @ 20443571961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_base_vseq.sv:217) [rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == * (* [*] vs * [*]) has 2 failures:
8.rv_dm_stress_all_with_rand_reset.83883977181909855768964271942248834741205291203206120648047319835402537385542
Line 260, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/8.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 937753367 ps: (rv_dm_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 937753367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.rv_dm_stress_all_with_rand_reset.14176535003860790618537745425166078971055466469909335057407488050659106536734
Line 268, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2283937219 ps: (rv_dm_base_vseq.sv:217) [uvm_test_top.env.virtual_sequencer.rv_dm_cmderr_not_supported_vseq] Check failed cfg.rv_dm_vif.cb.debug_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2283937219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (jtag_dmi_monitor.sv:112) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 2 failures:
17.rv_dm_stress_all.17827608891245308853568980969168357494161522999033267064571656141693696669918
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/17.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 662931350 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 662931350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
34.rv_dm_stress_all.113504704945191913211267523290077035719900712214955375828335750651247238212287
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 3317547755 ps: (jtag_dmi_monitor.sv:112) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
UVM_INFO @ 3317547755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:58) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == dm::jal(.rd(0), .imm(prog_buf_addr - whereto_addr)) (* [*] vs * [*]) has 2 failures:
28.rv_dm_stress_all.23001348530409255324365408146906701163024418816397080448639263941761610084339
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/28.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 8740525379 ps: (rv_dm_halt_resume_whereto_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == dm::jal(.rd(0), .imm(prog_buf_addr - whereto_addr)) (58720367 [0x380006f] vs 100663407 [0x600006f])
UVM_INFO @ 8740525379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.rv_dm_stress_all.26943187994809561635607305288790909835599767466277802193443101231851576398570
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/38.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14266473630 ps: (rv_dm_halt_resume_whereto_vseq.sv:58) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == dm::jal(.rd(0), .imm(prog_buf_addr - whereto_addr)) (58720367 [0x380006f] vs 100663407 [0x600006f])
UVM_INFO @ 14266473630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_sba_tl_access_vseq_lib.sv:120) [rv_dm_autoincr_sba_tl_access_vseq] Check failed (!req.timed_out) has 1 failures:
2.rv_dm_autoincr_sba_tl_access.101466926837470336758913123023985602771895812193135254188407079115765934833728
Line 274, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/2.rv_dm_autoincr_sba_tl_access/latest/run.log
UVM_ERROR @ 1353314970 ps: (rv_dm_sba_tl_access_vseq_lib.sv:120) [uvm_test_top.env.virtual_sequencer.rv_dm_autoincr_sba_tl_access_vseq] Check failed (!req.timed_out)
UVM_INFO @ 1353314970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
4.rv_dm_tap_fsm_rand_reset.31585213072682352822992870777692140763087381198946075292358950241765123143126
Line 283, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/4.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 13244397572 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_jtag_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_jtag_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 13244397572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_halted_vseq.sv:27) [rv_dm_mem_tl_access_halted_vseq] Check failed * == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (* [*] vs * [*]) has 1 failures:
6.rv_dm_stress_all_with_rand_reset.13627113816900533592503112891290736077225917733966223416453603580556590449156
Line 255, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 902390951 ps: (rv_dm_mem_tl_access_halted_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.rv_dm_mem_tl_access_halted_vseq] Check failed 1 == get_field_val(jtag_dmi_ral.dmstatus.anyhalted, r_data) (1 [0x1] vs 0 [0x0])
UVM_INFO @ 902390951 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_halt_resume_whereto_vseq.sv:42) [rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (* [*] vs * [*]) has 1 failures:
10.rv_dm_stress_all_with_rand_reset.64984665200332182133968772997349535504400998480704559393040455394517487510070
Line 259, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/10.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 993825616 ps: (rv_dm_halt_resume_whereto_vseq.sv:42) [uvm_test_top.env.virtual_sequencer.rv_dm_halt_resume_whereto_vseq] Check failed rdata == {exp_resume, exp_go} (0 [0x0] vs 1 [0x1])
UVM_INFO @ 993825616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:74) [scoreboard] Check failed item.dout == * (* [*] vs * [*]) has 1 failures:
25.rv_dm_stress_all_with_rand_reset.15006388716744020120916675548547621489907887814658871845662042260035245292934
Line 253, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/25.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 37204483 ps: (rv_dm_scoreboard.sv:74) [uvm_test_top.env.scoreboard] Check failed item.dout == 0 (8589934600 [0x200000008] vs 0 [0x0])
UVM_INFO @ 37204483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:73) [rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*]) has 1 failures:
33.rv_dm_stress_all_with_rand_reset.59164710055675575710487606192106135035042231781971292826522495019008200490551
Line 258, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/33.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2220603637 ps: (rv_dm_smoke_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 2220603637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_smoke_vseq.sv:73) [seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (* [*] vs * [*]) has 1 failures:
34.rv_dm_tap_fsm_rand_reset.43549511682006771604182381662436775835959785895771063446208205951446464805972
Line 263, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_tap_fsm_rand_reset/latest/run.log
UVM_ERROR @ 12093400408 ps: (rv_dm_smoke_vseq.sv:73) [uvm_test_top.env.virtual_sequencer.rv_dm_tap_fsm_vseq.seq] Check failed cfg.rv_dm_vif.cb.dmactive == data (0 [0x0] vs 1 [0x1])
UVM_INFO @ 12093400408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:250) [rv_dm_common_vseq] Timeout waiting tl_access : addr=* has 1 failures:
34.rv_dm_stress_all_with_rand_reset.9770586689870987509613665560587709362431273400451651497309913473578999490039
Line 268, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/34.rv_dm_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12917952313 ps: (cip_base_vseq.sv:250) [uvm_test_top.env.virtual_sequencer.rv_dm_common_vseq] Timeout waiting tl_access : addr=0xfb6467eb
UVM_INFO @ 12917952313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[*].get_reset() (* [*] vs * [*]) has 1 failures:
40.rv_dm_stress_all.89800428738398831304392896765884530170416591992312715372985759028920888286755
Line 251, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/40.rv_dm_stress_all/latest/run.log
UVM_ERROR @ 14538216872 ps: (rv_dm_jtag_dmi_dm_inactive_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.rv_dm_jtag_dmi_dm_inactive_vseq] Check failed rdata == jtag_dmi_ral.abstractdata[0].get_reset() (2958143569 [0xb051b051] vs 0 [0x0])
UVM_INFO @ 14538216872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---