Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg 100.00 1 100 1 64 64




Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0



Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 134 0 134 100.00
Crosses 3 0 3 100.00


Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mask 1 0 1 100.00 100 1 1 0
cp_opcode 3 0 3 100.00 100 1 1 0
cp_size 1 0 1 100.00 100 1 1 0
cp_source 129 0 129 100.00 100 1 1 0


Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
tl_a_chan_cov_cg_cc 3 0 3 100.00 100 1 1 0


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 179052 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 533930 1 T4 3 T28 2 T5 5



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 431015 1 T4 2 T5 8 T29 1
values[0x0] 138111 1 T4 3 T28 1 T29 1
values[0x1] 143856 1 T4 10 T28 1 T5 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 137633 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 575349 1 T4 5 T28 2 T5 7



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 3049 1 T58 2 T183 1 T17 1
valid_sources[0x01] 2935 1 T4 1 T13 1 T70 20
valid_sources[0x02] 3077 1 T13 1 T46 2 T70 16
valid_sources[0x03] 2412 1 T154 1 T184 4 T14 1
valid_sources[0x04] 2814 1 T56 5 T185 1 T70 16
valid_sources[0x05] 2626 1 T19 1 T186 1 T70 20
valid_sources[0x06] 2861 1 T13 2 T14 1 T162 3
valid_sources[0x07] 2915 1 T19 1 T59 2 T154 1
valid_sources[0x08] 3034 1 T14 1 T70 12 T63 2
valid_sources[0x09] 2732 1 T141 3 T70 14 T63 1
valid_sources[0x0a] 2641 1 T187 2 T70 18 T63 17
valid_sources[0x0b] 2835 1 T13 1 T14 1 T162 2
valid_sources[0x0c] 2497 1 T7 1 T30 2 T13 1
valid_sources[0x0d] 2905 1 T70 19 T63 10 T72 1
valid_sources[0x0e] 2531 1 T146 2 T183 1 T14 1
valid_sources[0x0f] 2692 1 T187 1 T70 18 T63 3
valid_sources[0x10] 2896 1 T59 1 T13 1 T70 23
valid_sources[0x11] 3089 1 T185 1 T70 27 T63 7
valid_sources[0x12] 3144 1 T19 1 T23 1 T70 25
valid_sources[0x13] 2968 1 T185 3 T70 18 T63 4
valid_sources[0x14] 3389 1 T59 1 T162 4 T70 14
valid_sources[0x15] 2449 1 T12 7 T55 1 T70 34
valid_sources[0x16] 2674 1 T55 1 T70 16 T63 13
valid_sources[0x17] 2764 1 T4 1 T13 1 T17 1
valid_sources[0x18] 2653 1 T20 4 T70 27 T63 3
valid_sources[0x19] 2621 1 T30 2 T24 2 T58 1
valid_sources[0x1a] 2674 1 T70 19 T63 1 T72 4
valid_sources[0x1b] 2838 1 T7 5 T15 1 T70 17
valid_sources[0x1c] 3031 1 T22 7 T148 3 T188 1
valid_sources[0x1d] 2811 1 T30 1 T13 1 T60 1
valid_sources[0x1e] 2670 1 T61 24 T183 1 T55 1
valid_sources[0x1f] 2879 1 T13 1 T55 1 T187 3
valid_sources[0x20] 3013 1 T55 1 T187 1 T70 29
valid_sources[0x21] 2530 1 T70 22 T63 11 T72 4
valid_sources[0x22] 2490 1 T58 1 T59 1 T154 2
valid_sources[0x23] 2897 1 T13 1 T55 1 T70 34
valid_sources[0x24] 2928 1 T30 1 T154 1 T189 2
valid_sources[0x25] 2578 1 T55 1 T70 25 T63 2
valid_sources[0x26] 2430 1 T30 2 T70 17 T63 3
valid_sources[0x27] 2912 1 T141 1 T70 27 T63 3
valid_sources[0x28] 2696 1 T19 2 T14 1 T70 18
valid_sources[0x29] 2854 1 T70 18 T63 1 T71 6
valid_sources[0x2a] 3702 1 T23 5 T55 1 T70 19
valid_sources[0x2b] 2672 1 T190 5 T70 12 T63 23
valid_sources[0x2c] 2836 1 T19 1 T70 24 T63 2
valid_sources[0x2d] 2880 1 T57 2 T162 1 T187 1
valid_sources[0x2e] 2900 1 T141 1 T38 1 T187 1
valid_sources[0x2f] 2623 1 T11 16 T12 2 T188 1
valid_sources[0x30] 2484 1 T55 1 T70 20 T63 6
valid_sources[0x31] 2498 1 T24 1 T183 1 T141 1
valid_sources[0x32] 2925 1 T59 1 T184 1 T14 1
valid_sources[0x33] 3033 1 T146 2 T70 16 T63 12
valid_sources[0x34] 2892 1 T58 1 T146 1 T13 1
valid_sources[0x35] 3209 1 T30 1 T154 1 T23 3
valid_sources[0x36] 2817 1 T58 1 T183 1 T70 23
valid_sources[0x37] 2664 1 T58 1 T59 1 T60 4
valid_sources[0x38] 2707 1 T154 1 T23 2 T13 1
valid_sources[0x39] 2578 1 T12 5 T14 1 T55 1
valid_sources[0x3a] 2899 1 T191 1 T70 29 T63 6
valid_sources[0x3b] 2939 1 T70 25 T63 8 T72 3
valid_sources[0x3c] 2580 1 T15 1 T192 8 T70 18
valid_sources[0x3d] 2856 1 T13 2 T183 1 T185 2
valid_sources[0x3e] 2723 1 T154 1 T10 1 T17 1
valid_sources[0x3f] 2824 1 T5 1 T14 1 T70 13
valid_sources[0x40] 2372 1 T154 1 T70 18 T63 7
valid_sources[0x41] 2631 1 T7 6 T70 16 T63 3
valid_sources[0x42] 2866 1 T15 2 T70 18 T63 6
valid_sources[0x43] 2596 1 T20 1 T55 1 T70 18
valid_sources[0x44] 2543 1 T154 1 T57 3 T70 18
valid_sources[0x45] 2609 1 T56 5 T189 3 T183 1
valid_sources[0x46] 2767 1 T148 2 T70 28 T63 2
valid_sources[0x47] 3029 1 T55 1 T185 3 T70 22
valid_sources[0x48] 2680 1 T30 3 T189 3 T13 1
valid_sources[0x49] 2634 1 T25 1 T10 1 T15 1
valid_sources[0x4a] 2929 1 T59 2 T13 1 T70 21
valid_sources[0x4b] 2884 1 T60 2 T55 1 T70 19
valid_sources[0x4c] 2723 1 T55 1 T70 21 T63 8
valid_sources[0x4d] 2850 1 T30 3 T70 18 T63 4
valid_sources[0x4e] 3194 1 T58 1 T70 21 T63 10
valid_sources[0x4f] 2685 1 T70 27 T63 5 T72 1
valid_sources[0x50] 2897 1 T189 1 T21 18 T70 20
valid_sources[0x51] 3048 1 T15 1 T187 1 T70 28
valid_sources[0x52] 2834 1 T12 6 T55 1 T70 29
valid_sources[0x53] 2549 1 T13 1 T183 1 T55 2
valid_sources[0x54] 2477 1 T70 17 T63 4 T72 4
valid_sources[0x55] 2494 1 T58 1 T154 1 T16 3
valid_sources[0x56] 2350 1 T4 1 T14 1 T185 1
valid_sources[0x57] 3114 1 T183 1 T17 2 T191 1
valid_sources[0x58] 3154 1 T19 1 T70 24 T63 4
valid_sources[0x59] 2877 1 T154 1 T146 6 T70 19
valid_sources[0x5a] 2468 1 T70 23 T63 4 T72 3
valid_sources[0x5b] 2431 1 T30 2 T19 1 T191 1
valid_sources[0x5c] 2870 1 T148 1 T187 1 T70 23
valid_sources[0x5d] 2738 1 T70 20 T63 2 T72 3
valid_sources[0x5e] 2825 1 T58 1 T10 1 T12 3
valid_sources[0x5f] 2626 1 T10 1 T183 1 T60 1
valid_sources[0x60] 2868 1 T17 1 T70 21 T63 5
valid_sources[0x61] 2938 1 T47 30 T187 2 T185 2
valid_sources[0x62] 2855 1 T56 2 T58 1 T55 1
valid_sources[0x63] 2692 1 T154 1 T55 2 T70 24
valid_sources[0x64] 2495 1 T5 1 T55 2 T70 22
valid_sources[0x65] 2767 1 T55 1 T70 15 T63 1
valid_sources[0x66] 3298 1 T34 1 T183 1 T55 1
valid_sources[0x67] 2376 1 T30 7 T14 1 T17 1
valid_sources[0x68] 2971 1 T30 1 T55 1 T70 26
valid_sources[0x69] 2723 1 T55 1 T185 1 T70 15
valid_sources[0x6a] 2590 1 T187 1 T70 21 T63 6
valid_sources[0x6b] 3244 1 T13 1 T17 1 T70 14
valid_sources[0x6c] 2580 1 T17 1 T141 1 T70 17
valid_sources[0x6d] 2893 1 T55 2 T70 25 T63 9
valid_sources[0x6e] 2912 1 T8 14 T30 2 T70 30
valid_sources[0x6f] 2525 1 T14 1 T187 1 T70 22
valid_sources[0x70] 2436 1 T14 1 T191 1 T70 18
valid_sources[0x71] 2780 1 T70 23 T63 4 T72 7
valid_sources[0x72] 2720 1 T193 1 T70 17 T72 2
valid_sources[0x73] 2853 1 T5 1 T17 1 T55 1
valid_sources[0x74] 2818 1 T150 1 T14 1 T70 11
valid_sources[0x75] 2794 1 T30 4 T189 2 T187 1
valid_sources[0x76] 2817 1 T7 2 T70 19 T63 1
valid_sources[0x77] 3154 1 T14 1 T41 30 T55 1
valid_sources[0x78] 3463 1 T70 18 T63 18 T72 3
valid_sources[0x79] 2523 1 T150 2 T55 1 T185 1
valid_sources[0x7a] 3185 1 T58 1 T70 16 T63 2
valid_sources[0x7b] 2854 1 T154 1 T188 1 T194 1
valid_sources[0x7c] 3052 1 T12 1 T162 2 T46 2
valid_sources[0x7d] 2485 1 T56 1 T70 20 T63 4
valid_sources[0x7e] 2877 1 T148 1 T162 1 T70 29
valid_sources[0x7f] 3409 1 T70 31 T63 3 T72 2
valid_sources[0x80] 2495 1 T5 1 T13 1 T55 1



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 261409 1 T5 5 T6 10 T30 2
values[0x0] all_enables biggest_size 136149 1 T4 1 T28 1 T29 1
values[0x1] all_enables biggest_size 136372 1 T4 2 T28 1 T7 2


Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_mask

Excluded/Illegal bins
NAMECOUNTSTATUS
others 4784 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_enables 20092 1 T1 1 T2 1 T3 4



Summary for Variable cp_opcode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_opcode

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] 9286 1 T73 3 T70 31 T63 165
values[0x0] 7615 1 T1 1 T3 2 T49 1
values[0x1] 7975 1 T2 1 T3 2 T50 1



Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 3677 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 21199 1 T1 1 T2 1 T3 4



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 64 1 T40 1 T71 1 T95 3
valid_sources[0x01] 80 1 T87 1 T91 3 T100 4
valid_sources[0x02] 96 1 T138 1 T14 1 T72 2
valid_sources[0x03] 112 1 T35 1 T195 1 T196 2
valid_sources[0x04] 78 1 T73 1 T72 2 T94 3
valid_sources[0x05] 71 1 T65 6 T165 1 T100 3
valid_sources[0x06] 306 1 T153 4 T138 1 T197 1
valid_sources[0x07] 87 1 T198 1 T87 3 T89 1
valid_sources[0x08] 62 1 T199 1 T44 2 T72 1
valid_sources[0x09] 146 1 T74 1 T183 6 T70 4
valid_sources[0x0a] 58 1 T72 3 T71 2 T88 1
valid_sources[0x0b] 53 1 T16 1 T195 1 T40 1
valid_sources[0x0c] 81 1 T10 1 T199 2 T187 5
valid_sources[0x0d] 75 1 T152 1 T88 2 T89 3
valid_sources[0x0e] 63 1 T159 1 T63 2 T72 2
valid_sources[0x0f] 67 1 T10 1 T71 1 T89 2
valid_sources[0x10] 89 1 T147 1 T72 1 T88 1
valid_sources[0x11] 73 1 T200 2 T72 2 T87 1
valid_sources[0x12] 89 1 T10 1 T201 1 T72 5
valid_sources[0x13] 89 1 T202 1 T203 1 T204 1
valid_sources[0x14] 81 1 T157 2 T89 1 T100 6
valid_sources[0x15] 123 1 T205 1 T21 1 T72 3
valid_sources[0x16] 123 1 T201 1 T63 1 T72 11
valid_sources[0x17] 76 1 T82 1 T72 1 T71 5
valid_sources[0x18] 111 1 T10 1 T206 2 T207 7
valid_sources[0x19] 100 1 T208 1 T209 1 T72 5
valid_sources[0x1a] 81 1 T210 1 T72 5 T71 2
valid_sources[0x1b] 65 1 T132 1 T88 2 T89 1
valid_sources[0x1c] 70 1 T81 3 T154 1 T72 1
valid_sources[0x1d] 93 1 T83 1 T63 1 T72 4
valid_sources[0x1e] 65 1 T7 1 T211 1 T186 1
valid_sources[0x1f] 80 1 T27 1 T212 1 T72 2
valid_sources[0x20] 134 1 T213 1 T214 1 T70 3
valid_sources[0x21] 65 1 T87 1 T89 5 T102 3
valid_sources[0x22] 76 1 T69 1 T72 1 T89 1
valid_sources[0x23] 69 1 T23 1 T215 1 T72 1
valid_sources[0x24] 71 1 T76 2 T40 1 T87 1
valid_sources[0x25] 71 1 T185 6 T72 2 T87 1
valid_sources[0x26] 56 1 T35 1 T216 1 T158 2
valid_sources[0x27] 85 1 T69 1 T146 1 T184 1
valid_sources[0x28] 82 1 T217 1 T218 1 T72 1
valid_sources[0x29] 67 1 T219 1 T15 2 T70 5
valid_sources[0x2a] 202 1 T17 1 T220 1 T72 2
valid_sources[0x2b] 103 1 T22 1 T221 1 T194 1
valid_sources[0x2c] 87 1 T35 1 T11 6 T72 2
valid_sources[0x2d] 73 1 T43 1 T72 2 T89 2
valid_sources[0x2e] 67 1 T82 1 T77 1 T218 1
valid_sources[0x2f] 64 1 T9 1 T222 4 T151 2
valid_sources[0x30] 96 1 T35 1 T12 1 T210 1
valid_sources[0x31] 64 1 T213 1 T72 1 T102 1
valid_sources[0x32] 104 1 T223 1 T70 1 T72 3
valid_sources[0x33] 81 1 T213 1 T72 2 T71 2
valid_sources[0x34] 77 1 T63 2 T72 2 T89 3
valid_sources[0x35] 79 1 T6 1 T144 3 T224 1
valid_sources[0x36] 63 1 T7 1 T225 1 T146 2
valid_sources[0x37] 147 1 T19 1 T157 2 T87 1
valid_sources[0x38] 120 1 T35 1 T226 1 T72 5
valid_sources[0x39] 71 1 T141 1 T72 2 T95 4
valid_sources[0x3a] 62 1 T72 1 T87 3 T89 1
valid_sources[0x3b] 85 1 T157 1 T190 9 T72 2
valid_sources[0x3c] 111 1 T37 1 T131 5 T7 1
valid_sources[0x3d] 105 1 T74 1 T154 1 T203 1
valid_sources[0x3e] 90 1 T201 1 T195 1 T87 1
valid_sources[0x3f] 71 1 T6 1 T56 1 T227 5
valid_sources[0x40] 70 1 T206 1 T72 3 T71 1
valid_sources[0x41] 45 1 T221 1 T72 1 T71 1
valid_sources[0x42] 108 1 T74 1 T70 2 T72 1
valid_sources[0x43] 99 1 T13 8 T72 6 T91 1
valid_sources[0x44] 92 1 T76 2 T6 1 T47 3
valid_sources[0x45] 118 1 T80 1 T56 1 T196 2
valid_sources[0x46] 68 1 T72 1 T71 1 T95 4
valid_sources[0x47] 81 1 T208 2 T184 1 T14 1
valid_sources[0x48] 57 1 T224 1 T147 3 T221 1
valid_sources[0x49] 94 1 T228 7 T72 4 T71 2
valid_sources[0x4a] 87 1 T132 3 T56 1 T184 1
valid_sources[0x4b] 128 1 T229 1 T22 3 T18 3
valid_sources[0x4c] 93 1 T61 4 T59 1 T197 3
valid_sources[0x4d] 77 1 T230 6 T72 3 T71 1
valid_sources[0x4e] 102 1 T12 1 T231 2 T40 1
valid_sources[0x4f] 72 1 T232 3 T43 2 T63 3
valid_sources[0x50] 99 1 T31 1 T5 1 T140 1
valid_sources[0x51] 69 1 T48 1 T233 7 T63 1
valid_sources[0x52] 88 1 T154 1 T221 1 T87 2
valid_sources[0x53] 90 1 T33 1 T6 1 T62 5
valid_sources[0x54] 68 1 T234 1 T235 1 T236 1
valid_sources[0x55] 538 1 T70 1 T72 1 T71 3
valid_sources[0x56] 194 1 T6 1 T154 1 T237 12
valid_sources[0x57] 75 1 T82 1 T238 3 T87 3
valid_sources[0x58] 66 1 T49 1 T214 1 T239 2
valid_sources[0x59] 89 1 T206 1 T221 1 T72 3
valid_sources[0x5a] 75 1 T12 1 T143 1 T70 1
valid_sources[0x5b] 72 1 T144 1 T72 2 T87 2
valid_sources[0x5c] 134 1 T154 1 T161 1 T70 1
valid_sources[0x5d] 77 1 T75 1 T236 1 T73 1
valid_sources[0x5e] 77 1 T200 2 T208 3 T210 2
valid_sources[0x5f] 84 1 T154 1 T63 1 T72 3
valid_sources[0x60] 92 1 T240 1 T89 3 T92 1
valid_sources[0x61] 121 1 T207 3 T63 52 T72 1
valid_sources[0x62] 73 1 T6 1 T241 1 T72 3
valid_sources[0x63] 90 1 T196 2 T72 2 T89 3
valid_sources[0x64] 126 1 T35 1 T80 1 T213 1
valid_sources[0x65] 121 1 T70 2 T88 1 T90 1
valid_sources[0x66] 54 1 T242 1 T89 2 T92 2
valid_sources[0x67] 68 1 T22 1 T71 1 T89 1
valid_sources[0x68] 90 1 T243 1 T209 1 T42 1
valid_sources[0x69] 84 1 T35 2 T141 2 T72 1
valid_sources[0x6a] 79 1 T244 11 T89 1 T96 1
valid_sources[0x6b] 78 1 T145 1 T245 1 T70 2
valid_sources[0x6c] 99 1 T148 8 T246 1 T72 1
valid_sources[0x6d] 184 1 T4 7 T15 4 T209 1
valid_sources[0x6e] 207 1 T37 1 T63 84 T72 2
valid_sources[0x6f] 78 1 T72 5 T87 1 T89 1
valid_sources[0x70] 93 1 T88 4 T89 2 T97 2
valid_sources[0x71] 54 1 T12 2 T89 1 T100 2
valid_sources[0x72] 87 1 T57 1 T197 1 T209 1
valid_sources[0x73] 112 1 T214 1 T247 14 T17 4
valid_sources[0x74] 82 1 T72 3 T87 14 T88 1
valid_sources[0x75] 318 1 T199 2 T72 3 T89 3
valid_sources[0x76] 60 1 T248 1 T206 1 T201 1
valid_sources[0x77] 107 1 T35 1 T74 1 T34 1
valid_sources[0x78] 78 1 T72 2 T89 2 T96 1
valid_sources[0x79] 244 1 T209 1 T63 1 T72 3
valid_sources[0x7a] 107 1 T149 1 T158 1 T71 1
valid_sources[0x7b] 115 1 T8 1 T188 3 T72 1
valid_sources[0x7c] 73 1 T249 1 T250 1 T88 1
valid_sources[0x7d] 96 1 T74 1 T154 1 T251 1
valid_sources[0x7e] 78 1 T146 1 T152 1 T163 1
valid_sources[0x7f] 53 1 T195 1 T63 2 T71 1
valid_sources[0x80] 122 1 T166 1 T72 6 T100 5



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 6497 1 T73 1 T70 14 T63 151
values[0x0] all_enables biggest_size 6886 1 T1 1 T3 2 T49 1
values[0x1] all_enables biggest_size 6709 1 T2 1 T3 2 T50 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%