Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block] 100.00 1 100 1 64 64




Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 223634 1 T4 12 T5 4 T29 1
full_word 535859 1 T4 3 T28 2 T5 5



Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 759193 1 T4 15 T28 2 T5 9
auto[TlIntgErrCmd] 102 1 T70 4 T88 3 T104 7
auto[TlIntgErrData] 103 1 T70 4 T88 2 T104 8
auto[TlIntgErrBoth] 95 1 T70 2 T88 5 T104 5



Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 433289 1 T4 2 T5 8 T29 1
auto[1] 326204 1 T4 13 T28 2 T5 1



Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 171515 1 T4 2 T5 3 T29 1
auto[TlIntgErrNone] partial auto[1] 51843 1 T4 10 T5 1 T7 16
auto[TlIntgErrNone] full_word auto[0] 261632 1 T5 5 T6 10 T30 2
auto[TlIntgErrNone] full_word auto[1] 274203 1 T4 3 T28 2 T29 1
auto[TlIntgErrCmd] partial auto[0] 40 1 T70 1 T88 2 T104 2
auto[TlIntgErrCmd] partial auto[1] 54 1 T70 3 T88 1 T104 5
auto[TlIntgErrCmd] full_word auto[0] 5 1 T174 1 T175 1 T177 1
auto[TlIntgErrCmd] full_word auto[1] 3 1 T173 1 T177 2 - -
auto[TlIntgErrData] partial auto[0] 44 1 T70 1 T88 2 T104 4
auto[TlIntgErrData] partial auto[1] 50 1 T70 3 T104 3 T172 5
auto[TlIntgErrData] full_word auto[0] 5 1 T104 1 T172 1 T168 1
auto[TlIntgErrData] full_word auto[1] 4 1 T171 1 T169 2 T178 1
auto[TlIntgErrBoth] partial auto[0] 46 1 T70 2 T88 4 T104 2
auto[TlIntgErrBoth] partial auto[1] 42 1 T88 1 T104 3 T134 5
auto[TlIntgErrBoth] full_word auto[0] 2 1 T174 1 T176 1 - -
auto[TlIntgErrBoth] full_word auto[1] 5 1 T172 1 T179 1 T180 1

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