Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	132403110	16147	0	0
late_debug_enable_rd_A	132403110	3635	0	0
late_debug_enable_regwen_rd_A	132403110	1646	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132403110	16147	0	0
T63	139692	1669	0	0
T70	181633	3	0	0
T71	20173	21	0	0
T72	26963	539	0	0
T87	15885	51	0	0
T88	103214	2	0	0
T89	17502	663	0	0
T90	21509	170	0	0
T91	27464	467	0	0
T92	4759	248	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132403110	3635	0	0
T71	20173	25	0	0
T88	103214	33	0	0
T89	17502	251	0	0
T91	27464	190	0	0
T96	8140	10	0	0
T99	10124	14	0	0
T100	410103	1930	0	0
T134	111778	67	0	0
T135	57694	5	0	0
T136	7755	13	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	132403110	1646	0	0
T71	20173	16	0	0
T88	103214	44	0	0
T89	17502	218	0	0
T91	27464	155	0	0
T96	8140	4	0	0
T99	10124	12	0	0
T124	21060	37	0	0
T134	111778	116	0	0
T135	57694	10	0	0
T136	7755	9	0	0