Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	75.00						75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00						75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	68001070	6259502	0	0
MemTLResponseWithoutDebugIsError_A	68001070	12	0	0
NdmResetAckNeedsDebug_A	68001070	0	0	0
SbaTLRequestNeedsDebug_A	68001070	14168	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	6259502	0	0
T4	237938	94056	0	0
T5	6204	4983	0	0
T6	0	32423	0	0
T7	0	62257	0	0
T8	0	36599	0	0
T9	41770	0	0	0
T24	0	32421	0	0
T26	847375	0	0	0
T27	10040	0	0	0
T28	18225	0	0	0
T30	0	174821	0	0
T31	393511	0	0	0
T32	0	9079	0	0
T33	0	14716	0	0
T34	0	4485	0	0
T35	7522	0	0	0
T36	391165	0	0	0
T37	4002	0	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	12	0	0
T38	1610	2	0	0
T39	0	10	0	0
T40	4600	0	0	0
T41	92372	0	0	0
T42	719362	0	0	0
T43	6009	0	0	0
T44	129213	0	0	0
T45	814613	0	0	0
T46	76461	0	0	0
T47	190013	0	0	0
T48	104878	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	14168	0	0
T1	239806	15	0	0
T2	144954	71	0	0
T3	160057	149	0	0
T4	237938	0	0	0
T26	847375	154	0	0
T27	10040	32	0	0
T31	0	3138	0	0
T35	7522	0	0	0
T36	391165	31	0	0
T49	36241	21	0	0
T50	66651	60	0	0
T51	0	89	0	0