Module Definition
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Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_clock_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_prim_rst_n_mux2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_rst_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 9947132 9945802 0 0
selKnown1 74969089 74967755 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 9947132 9945802 0 0
T1 14894 14892 0 0
T2 18620 18618 0 0
T3 41360 41356 0 0
T4 29348 29344 0 0
T6 0 12 0 0
T7 0 18 0 0
T26 91249 91245 0 0
T27 15367 15363 0 0
T28 2 0 0 0
T30 0 8 0 0
T31 2 0 0 0
T35 297 293 0 0
T36 33608 33604 0 0
T49 26622 26618 0 0
T50 10823 10819 0 0
T51 0 12 0 0
T66 0 40 0 0
T69 0 4 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 74969089 74967755 0 0
T1 247253 247251 0 0
T2 154264 154262 0 0
T3 180741 180737 0 0
T4 252614 252610 0 0
T6 0 12 0 0
T7 0 6 0 0
T26 893005 893001 0 0
T27 17725 17721 0 0
T28 2 0 0 0
T30 0 4 0 0
T31 2 0 0 0
T35 7671 7667 0 0
T36 407970 407966 0 0
T49 49553 49549 0 0
T50 72063 72059 0 0
T51 0 12 0 0
T66 0 40 0 0
T69 0 4 0 0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2978427 2978203 0 0
selKnown1 68001070 68000844 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2978427 2978203 0 0
T1 7447 7446 0 0
T2 9310 9309 0 0
T3 20676 20675 0 0
T4 14664 14663 0 0
T26 45618 45617 0 0
T27 7681 7680 0 0
T35 147 146 0 0
T36 16803 16802 0 0
T49 13310 13309 0 0
T50 5410 5409 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 68001070 68000844 0 0
T1 239806 239805 0 0
T2 144954 144953 0 0
T3 160057 160056 0 0
T4 237938 237937 0 0
T26 847375 847374 0 0
T27 10040 10039 0 0
T35 7522 7521 0 0
T36 391165 391164 0 0
T49 36241 36240 0 0
T50 66651 66650 0 0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 747 523 0 0
selKnown1 615 389 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 747 523 0 0
T3 4 3 0 0
T4 10 9 0 0
T6 0 6 0 0
T7 0 9 0 0
T26 6 5 0 0
T27 2 1 0 0
T28 1 0 0 0
T30 0 2 0 0
T31 1 0 0 0
T35 1 0 0 0
T36 1 0 0 0
T49 1 0 0 0
T50 1 0 0 0
T51 0 6 0 0
T66 0 20 0 0
T69 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 615 389 0 0
T3 4 3 0 0
T4 6 5 0 0
T6 0 6 0 0
T7 0 3 0 0
T26 6 5 0 0
T27 2 1 0 0
T28 1 0 0 0
T30 0 2 0 0
T31 1 0 0 0
T35 1 0 0 0
T36 1 0 0 0
T49 1 0 0 0
T50 1 0 0 0
T51 0 6 0 0
T66 0 20 0 0
T69 0 2 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 6965982 6965540 0 0
selKnown1 6965760 6965320 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 6965982 6965540 0 0
T1 7447 7446 0 0
T2 9310 9309 0 0
T3 20676 20675 0 0
T4 14664 14663 0 0
T26 45619 45618 0 0
T27 7682 7681 0 0
T35 148 147 0 0
T36 16803 16802 0 0
T49 13310 13309 0 0
T50 5411 5410 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 6965760 6965320 0 0
T1 7447 7446 0 0
T2 9310 9309 0 0
T3 20676 20675 0 0
T4 14664 14663 0 0
T26 45618 45617 0 0
T27 7681 7680 0 0
T35 147 146 0 0
T36 16803 16802 0 0
T49 13310 13309 0 0
T50 5410 5409 0 0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1976 1536 0 0
selKnown1 1644 1202 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1976 1536 0 0
T3 4 3 0 0
T4 10 9 0 0
T6 0 6 0 0
T7 0 9 0 0
T26 6 5 0 0
T27 2 1 0 0
T28 1 0 0 0
T30 0 6 0 0
T31 1 0 0 0
T35 1 0 0 0
T36 1 0 0 0
T49 1 0 0 0
T50 1 0 0 0
T51 0 6 0 0
T66 0 20 0 0
T69 0 2 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 1644 1202 0 0
T3 4 3 0 0
T4 6 5 0 0
T6 0 6 0 0
T7 0 3 0 0
T26 6 5 0 0
T27 2 1 0 0
T28 1 0 0 0
T30 0 2 0 0
T31 1 0 0 0
T35 1 0 0 0
T36 1 0 0 0
T49 1 0 0 0
T50 1 0 0 0
T51 0 6 0 0
T66 0 20 0 0
T69 0 2 0 0

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