Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync_lc_hw_debug_en	100.00	100.00					100.00
tb.dut.u_prim_lc_sync_lc_dft_en	100.00	100.00					100.00
tb.dut.u_lc_en_sync_copies	100.00	100.00					100.00
tb.dut.u_pm_en_sync	100.00	100.00					100.00
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync	100.00	100.00					100.00
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_lc_sync_lc_dft_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_en_sync_copies

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_pm_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
68.13	86.27	72.22		57.14	75.00	50.00	u_tlul_lc_gate_sba

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
82.66	98.04	77.78		100.00	87.50	50.00	u_tlul_lc_gate_rom

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sync_lc_hw_debug_en

SCORE	LINE
100.00	100.00

tb.dut.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_lc_en_sync_copies

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	5	5

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_pm_en_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	3	3

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1356	1356	0	0
OutputsKnown_A	408006420	407760264	0	0
gen_flops.OutputDelay_A	204003210	203874597	0	2034
gen_no_flops.OutputDelay_A	204003210	203880132	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1356	1356	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T26	6	6	0	0
T27	6	6	0	0
T35	6	6	0	0
T36	6	6	0	0
T49	6	6	0	0
T50	6	6	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	408006420	407760264	0	0
T1	1438836	1438458	0	0
T2	869724	869364	0	0
T3	960342	958830	0	0
T4	1427628	1424904	0	0
T26	5084250	5082084	0	0
T27	60240	59364	0	0
T35	45132	44796	0	0
T36	2346990	2346570	0	0
T49	217446	217134	0	0
T50	399906	399426	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204003210	203874597	0	2034
T1	719418	719220	0	9
T2	434862	434673	0	9
T3	480171	479379	0	9
T4	713814	712398	0	9
T26	2542125	2540988	0	9
T27	30120	29664	0	9
T35	22566	22389	0	9
T36	1173495	1173276	0	9
T49	108723	108558	0	9
T50	199953	199704	0	9

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	204003210	203880132	0	0
T1	719418	719229	0	0
T2	434862	434682	0	0
T3	480171	479415	0	0
T4	713814	712452	0	0
T26	2542125	2541042	0	0
T27	30120	29682	0	0
T35	22566	22398	0	0
T36	1173495	1173285	0	0
T49	108723	108567	0	0
T50	199953	199713	0	0

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_hw_debug_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	226	226	0	0
OutputsKnown_A	68001070	67960044	0	0
gen_flops.OutputDelay_A	68001070	67958199	0	678

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226	226	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67960044	0	0
T1	239806	239743	0	0
T2	144954	144894	0	0
T3	160057	159805	0	0
T4	237938	237484	0	0
T26	847375	847014	0	0
T27	10040	9894	0	0
T35	7522	7466	0	0
T36	391165	391095	0	0
T49	36241	36189	0	0
T50	66651	66571	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67958199	0	678
T1	239806	239740	0	3
T2	144954	144891	0	3
T3	160057	159793	0	3
T4	237938	237466	0	3
T26	847375	846996	0	3
T27	10040	9888	0	3
T35	7522	7463	0	3
T36	391165	391092	0	3
T49	36241	36186	0	3
T50	66651	66568	0	3

Line Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	1	1

---

Assert Coverage for Instance : tb.dut.u_prim_lc_sync_lc_dft_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	226	226	0	0
OutputsKnown_A	68001070	67960044	0	0
gen_flops.OutputDelay_A	68001070	67958199	0	678

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226	226	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67960044	0	0
T1	239806	239743	0	0
T2	144954	144894	0	0
T3	160057	159805	0	0
T4	237938	237484	0	0
T26	847375	847014	0	0
T27	10040	9894	0	0
T35	7522	7466	0	0
T36	391165	391095	0	0
T49	36241	36189	0	0
T50	66651	66571	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67958199	0	678
T1	239806	239740	0	3
T2	144954	144891	0	3
T3	160057	159793	0	3
T4	237938	237466	0	3
T26	847375	846996	0	3
T27	10040	9888	0	3
T35	7522	7463	0	3
T36	391165	391092	0	3
T49	36241	36186	0	3
T50	66651	66568	0	3

Line Coverage for Instance : tb.dut.u_lc_en_sync_copies

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	5	5

---

Assert Coverage for Instance : tb.dut.u_lc_en_sync_copies

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	226	226	0	0
OutputsKnown_A	68001070	67960044	0	0
gen_no_flops.OutputDelay_A	68001070	67960044	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226	226	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67960044	0	0
T1	239806	239743	0	0
T2	144954	144894	0	0
T3	160057	159805	0	0
T4	237938	237484	0	0
T26	847375	847014	0	0
T27	10040	9894	0	0
T35	7522	7466	0	0
T36	391165	391095	0	0
T49	36241	36189	0	0
T50	66651	66571	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67960044	0	0
T1	239806	239743	0	0
T2	144954	144894	0	0
T3	160057	159805	0	0
T4	237938	237484	0	0
T26	847375	847014	0	0
T27	10040	9894	0	0
T35	7522	7466	0	0
T36	391165	391095	0	0
T49	36241	36189	0	0
T50	66651	66571	0	0

Line Coverage for Instance : tb.dut.u_pm_en_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
106	3	3

---

Assert Coverage for Instance : tb.dut.u_pm_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	226	226	0	0
OutputsKnown_A	68001070	67960044	0	0
gen_flops.OutputDelay_A	68001070	67958199	0	678

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226	226	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67960044	0	0
T1	239806	239743	0	0
T2	144954	144894	0	0
T3	160057	159805	0	0
T4	237938	237484	0	0
T26	847375	847014	0	0
T27	10040	9894	0	0
T35	7522	7466	0	0
T36	391165	391095	0	0
T49	36241	36189	0	0
T50	66651	66571	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67958199	0	678
T1	239806	239740	0	3
T2	144954	144891	0	3
T3	160057	159793	0	3
T4	237938	237466	0	3
T26	847375	846996	0	3
T27	10040	9888	0	3
T35	7522	7463	0	3
T36	391165	391092	0	3
T49	36241	36186	0	3
T50	66651	66568	0	3

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	226	226	0	0
OutputsKnown_A	68001070	67960044	0	0
gen_no_flops.OutputDelay_A	68001070	67960044	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226	226	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67960044	0	0
T1	239806	239743	0	0
T2	144954	144894	0	0
T3	160057	159805	0	0
T4	237938	237484	0	0
T26	847375	847014	0	0
T27	10040	9894	0	0
T35	7522	7466	0	0
T36	391165	391095	0	0
T49	36241	36189	0	0
T50	66651	66571	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67960044	0	0
T1	239806	239743	0	0
T2	144954	144894	0	0
T3	160057	159805	0	0
T4	237938	237484	0	0
T26	847375	847014	0	0
T27	10040	9894	0	0
T35	7522	7466	0	0
T36	391165	391095	0	0
T49	36241	36189	0	0
T50	66651	66571	0	0

Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' or '../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
84		unreachable
85		unreachable
87		unreachable
93	1	1
106	2	2

---

Assert Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	226	226	0	0
OutputsKnown_A	68001070	67960044	0	0
gen_no_flops.OutputDelay_A	68001070	67960044	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226	226	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T35	1	1	0	0
T36	1	1	0	0
T49	1	1	0	0
T50	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67960044	0	0
T1	239806	239743	0	0
T2	144954	144894	0	0
T3	160057	159805	0	0
T4	237938	237484	0	0
T26	847375	847014	0	0
T27	10040	9894	0	0
T35	7522	7466	0	0
T36	391165	391095	0	0
T49	36241	36189	0	0
T50	66651	66571	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68001070	67960044	0	0
T1	239806	239743	0	0
T2	144954	144894	0	0
T3	160057	159805	0	0
T4	237938	237484	0	0
T26	847375	847014	0	0
T27	10040	9894	0	0
T35	7522	7466	0	0
T36	391165	391095	0	0
T49	36241	36189	0	0
T50	66651	66571	0	0