Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	134141546	18921	0	0
late_debug_enable_rd_A	134141546	4175	0	0
late_debug_enable_regwen_rd_A	134141546	2201	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134141546	18921	0	0
T60	93524	2	0	0
T61	13839	34	0	0
T62	80898	7	0	0
T63	21690	780	0	0
T64	10397	376	0	0
T90	12846	543	0	0
T91	306715	1	0	0
T92	21706	53	0	0
T93	44374	3	0	0
T94	158979	3	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134141546	4175	0	0
T60	93524	65	0	0
T61	13839	38	0	0
T63	21690	179	0	0
T65	19614	19	0	0
T94	158979	49	0	0
T100	38504	47	0	0
T116	396097	617	0	0
T118	385504	1926	0	0
T141	13652	87	0	0
T142	341444	11	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	134141546	2201	0	0
T53	953498	210	0	0
T60	93524	56	0	0
T61	13839	49	0	0
T63	21690	169	0	0
T65	19614	21	0	0
T94	158979	55	0	0
T100	38504	10	0	0
T116	396097	620	0	0
T141	13652	87	0	0
T142	341444	2	0	0