Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_dm
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.12 96.97 59.57 91.58 100.00 87.50

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 87.12 96.97 59.57 91.58 100.00 87.50



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.12 96.97 59.57 91.58 100.00 87.50


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
87.20 95.32 80.00 89.42 74.36 85.67 98.42


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
dap 84.39 98.36 86.58 68.00 94.02 75.00
enable_checker 87.50 100.00 75.00
gen_alert_tx[0].u_prim_alert_sender 83.33 83.33
i_tlul_adapter_reg 93.27 99.00 80.90 93.33 93.10 100.00
rv_dm_regs_csr_assert 100.00 100.00
tl_adapter_host_sba 95.14 100.00 100.00 75.71 100.00 100.00
tlul_assert_device_mem 95.24 100.00 85.71 100.00
tlul_assert_device_regs 95.24 100.00 85.71 100.00
tlul_assert_host_sba 94.30 100.00 85.71 97.18
u_dm_top 84.37 88.16 66.84 92.86 73.99 100.00
u_lc_en_sync_copies 100.00 100.00 100.00
u_pm_en_sync 100.00 100.00 100.00 100.00
u_prim_clock_mux2 85.19 100.00 55.56 100.00
u_prim_flop_2sync_lc_rst_assert 100.00 100.00 100.00
u_prim_flop_2sync_lc_rst_sync 100.00 100.00 100.00
u_prim_lc_sync_lc_dft_en 100.00 100.00 100.00 100.00
u_prim_lc_sync_lc_hw_debug_en 100.00 100.00 100.00 100.00
u_prim_mubi32_sync_late_debug_enable 100.00 100.00 100.00
u_prim_mubi8_sync_otp_dis_rv_dm_late_debug 100.00 100.00 100.00 100.00
u_prim_rst_n_mux2 85.19 100.00 55.56 100.00
u_reg_regs 98.19 98.69 98.71 93.55 100.00 100.00
u_tlul_lc_gate_rom 91.90 99.21 82.14 100.00 90.62 87.50
u_tlul_lc_gate_sba 74.11 89.76 64.29 57.14 71.88 87.50


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rv_dm
Line No.TotalCoveredPercent
TOTAL333296.97
CONT_ASSIGN12211100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12811100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN154100.00
CONT_ASSIGN23611100.00
CONT_ASSIGN23711100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN23911100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN28811100.00
CONT_ASSIGN28911100.00
ALWAYS3201111100.00
CONT_ASSIGN34511100.00
CONT_ASSIGN43211100.00
CONT_ASSIGN43811100.00
CONT_ASSIGN44011100.00
CONT_ASSIGN44611100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN55111100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
122 1 1
123 1 1
128 1 1
131 1 1
154 0 1
236 1 1
237 1 1
239 4 4
278 1 1
288 1 1
289 1 1
320 1 1
321 1 1
322 1 1
325 1 1
326 1 1
327 1 1
328 1 1
MISSING_ELSE
331 1 1
332 1 1
333 1 1
334 1 1
MISSING_ELSE
345 1 1
432 1 1
438 1 1
440 1 1
446 1 1
447 1 1
523 1 1
551 1 1


Cond Coverage for Module : rv_dm
TotalCoveredPercent
Conditions472859.57
Logical472859.57
Non-Logical00
Event00

 LINE       128
 EXPRESSION (regs_intg_error | rom_intg_error | sba_gate_intg_error | rom_gate_intg_error)
             -------1-------   -------2------   ---------3---------   ---------4---------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100Not Covered
1000CoveredT49,T50,T51

 LINE       131
 SUB-EXPRESSION (regs_reg2hw.alert_test.q & regs_reg2hw.alert_test.qe)
                 ------------1-----------   ------------2------------
-1--2-StatusTests
01CoveredT43,T45,T57
10CoveredT1,T43,T4
11CoveredT43,T36,T45

 LINE       289
 EXPRESSION (ndmreset_req_qual & reset_req_en)
             --------1--------   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT7,T30,T31
11CoveredT4,T7,T21

 LINE       325
 EXPRESSION (ndmreset_req && ((!ndmreset_pending_q)))
             ------1-----    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT4,T7,T21
11CoveredT4,T7,T21

 LINE       327
 EXPRESSION (ndmreset_ack && ndmreset_pending_q)
             ------1-----    ---------2--------
-1--2-StatusTests
01CoveredT4,T7,T21
10Not Covered
11Not Covered

 LINE       331
 EXPRESSION (ndmreset_pending_q && lc_rst_asserted)
             ---------1--------    -------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       333
 EXPRESSION (ndmreset_ack && lc_rst_pending_q)
             ------1-----    --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       345
 EXPRESSION (ndmreset_pending_q && lc_rst_pending_q && ((!ndmreset_req)) && ((!lc_rst_asserted)) && reset_req_en)
             ---------1--------    --------2-------    --------3--------    ----------4---------    ------5-----
-1--2--3--4--5-StatusTests
01111Not Covered
10111Not Covered
11011Not Covered
11101Not Covered
11110Not Covered
11111Not Covered

 LINE       440
 EXPRESSION (debug_req & debug_req_en)
             ----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT47,T48
11CoveredT4,T7,T5

 LINE       476
 EXPRESSION (dmi_req_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

 LINE       476
 EXPRESSION (dmi_rsp_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       551
 EXPRESSION (device_we || device_re)
             ----1----    ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT34,T7,T8
10CoveredT4,T7,T5

 LINE       567
 EXPRESSION (dmi_req_valid & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T3

 LINE       567
 EXPRESSION (dmi_rsp_ready & dmi_en)
             ------1------   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T4
11CoveredT1,T2,T3

Toggle Coverage for Module : rv_dm
TotalCoveredPercent
Totals 98 77 78.57
Total Bits 1140 1044 91.58
Total Bits 0->1 570 522 91.58
Total Bits 1->0 570 522 91.58

Ports 98 77 78.57
Port Bits 1140 1044 91.58
Port Bits 0->1 570 522 91.58
Port Bits 1->0 570 522 91.58

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_lc_i No No No INPUT
rst_ni Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
rst_lc_ni No No No INPUT
next_dm_addr_i[31:0] Unreachable Unreachable Unreachable INPUT
lc_hw_debug_en_i[3:0] Yes Yes T7,T30,T31 Yes T7,T30,T31 INPUT
lc_dft_en_i[3:0] No No No INPUT
pinmux_hw_debug_en_i[3:0] Yes Yes T4,T7,T5 Yes T4,T7,T5 INPUT
otp_dis_rv_dm_late_debug_i[7:0] Yes Yes T4,T7,T5 Yes T4,T6,T21 INPUT
scanmode_i[3:0] No No No INPUT
scan_rst_ni Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
ndmreset_req_o Yes Yes T4,T7,T21 Yes T4,T7,T21 OUTPUT
dmactive_o Yes Yes T1,T2,T4 Yes T1,T2,T3 OUTPUT
debug_req_o Yes Yes T4,T7,T5 Yes T4,T7,T5 OUTPUT
unavailable_i Yes Yes T4,T7,T5 Yes T4,T7,T5 INPUT
regs_tl_d_i.d_ready Yes Yes T1,T2,T43 Yes T1,T2,T3 INPUT
regs_tl_d_i.a_user.data_intg[6:0] Yes Yes T1,T43,T4 Yes T1,T43,T4 INPUT
regs_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T43 Yes T1,T43,T4 INPUT
regs_tl_d_i.a_user.instr_type[3:0] Yes Yes T57,T58,T59 Yes T57,T58,T59 INPUT
regs_tl_d_i.a_user.rsvd[4:0] Yes Yes T57,T58,T59 Yes T57,T59,T5 INPUT
regs_tl_d_i.a_data[31:0] Yes Yes T43,T4,T45 Yes T1,T43,T4 INPUT
regs_tl_d_i.a_mask[3:0] Yes Yes T57,T58,T59 Yes T57,T58,T59 INPUT
regs_tl_d_i.a_address[31:0] Yes Yes T57,T58,T59 Yes T57,T59,T5 INPUT
regs_tl_d_i.a_source[7:0] Yes Yes T43,T4,T45 Yes T43,T4,T45 INPUT
regs_tl_d_i.a_size[1:0] Yes Yes T43,T45,T57 Yes T43,T45,T57 INPUT
regs_tl_d_i.a_param[2:0] Yes Yes T57,T58,T59 Yes T57,T58,T59 INPUT
regs_tl_d_i.a_opcode[2:0] Yes Yes T1,T2,T43 Yes T1,T43,T4 INPUT
regs_tl_d_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
regs_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
regs_tl_d_o.d_error Yes Yes T60,T61,T62 Yes T63,T60,T64 OUTPUT
regs_tl_d_o.d_user.data_intg[6:0] Yes Yes T65,T66,T67 Yes T65,T66,T67 OUTPUT
regs_tl_d_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T43 Yes T1,T2,T3 OUTPUT
regs_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
regs_tl_d_o.d_data[31:0] Yes Yes T1,T2,T4 Yes T1,T2,T3 OUTPUT
regs_tl_d_o.d_sink No No No OUTPUT
regs_tl_d_o.d_source[7:0] Yes Yes T1,T2,T43 Yes T1,T2,T3 OUTPUT
regs_tl_d_o.d_size[1:0] Yes Yes T43,T45,T57 Yes T43,T45,T57 OUTPUT
regs_tl_d_o.d_param[2:0] No No No OUTPUT
regs_tl_d_o.d_opcode[0] Yes Yes *T63,*T65,*T66 Yes T63,T65,T66 OUTPUT
regs_tl_d_o.d_opcode[2:1] No No No OUTPUT
regs_tl_d_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_i.d_ready Yes Yes T1,T2,T43 Yes T1,T2,T3 INPUT
mem_tl_d_i.a_user.data_intg[6:0] Yes Yes T2,T36,T34 Yes T3,T44,T34 INPUT
mem_tl_d_i.a_user.cmd_intg[6:0] Yes Yes T4,T44,T34 Yes T2,T4,T36 INPUT
mem_tl_d_i.a_user.instr_type[3:0] Yes Yes T2,T34,T68 Yes T44,T36,T34 INPUT
mem_tl_d_i.a_user.rsvd[4:0] Yes Yes T36,T34,T27 Yes T2,T34,T27 INPUT
mem_tl_d_i.a_data[31:0] Yes Yes T2,T34,T7 Yes T34,T69,T27 INPUT
mem_tl_d_i.a_mask[3:0] Yes Yes T2,T34,T7 Yes T2,T36,T34 INPUT
mem_tl_d_i.a_address[31:0] Yes Yes T2,T34,T27 Yes T44,T34,T69 INPUT
mem_tl_d_i.a_source[7:0] Yes Yes T4,T44,T34 Yes T2,T4,T36 INPUT
mem_tl_d_i.a_size[1:0] Yes Yes T3,T4,T44 Yes T2,T4,T34 INPUT
mem_tl_d_i.a_param[2:0] Yes Yes T2,T44,T34 Yes T2,T3,T34 INPUT
mem_tl_d_i.a_opcode[2:0] Yes Yes T2,T4,T34 Yes T2,T3,T4 INPUT
mem_tl_d_i.a_valid Yes Yes T4,T34,T7 Yes T4,T34,T7 INPUT
mem_tl_d_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
mem_tl_d_o.d_error Yes Yes T1,T2,T3 Yes T1,T2,T4 OUTPUT
mem_tl_d_o.d_user.data_intg[6:0] Yes Yes T34,T8,T9 Yes T34,T8,T9 OUTPUT
mem_tl_d_o.d_user.rsp_intg[5:0] Yes Yes T4,*T7,*T5 Yes T4,T7,T5 OUTPUT
mem_tl_d_o.d_user.rsp_intg[6] No No No OUTPUT
mem_tl_d_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T4 OUTPUT
mem_tl_d_o.d_sink No No No OUTPUT
mem_tl_d_o.d_source[7:0] Yes Yes T4,T7,T5 Yes T4,T34,T7 OUTPUT
mem_tl_d_o.d_size[1:0] Yes Yes T4,T7,T5 Yes T4,T7,T5 OUTPUT
mem_tl_d_o.d_param[2:0] No No No OUTPUT
mem_tl_d_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T4 OUTPUT
mem_tl_d_o.d_opcode[2:1] No No No OUTPUT
mem_tl_d_o.d_valid Yes Yes T4,T34,T7 Yes T4,T34,T7 OUTPUT
sba_tl_h_o.d_ready Yes Yes T1,T2,T4 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[0] Yes Yes *T1,*T2,*T4 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.instr_type[2:1] No No No OUTPUT
sba_tl_h_o.a_user.instr_type[3] Yes Yes T1,T2,T4 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_user.rsvd[4:0] No No No OUTPUT
sba_tl_h_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_address[1:0] No No No OUTPUT
sba_tl_h_o.a_address[31:2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_source[7:0] No No No OUTPUT
sba_tl_h_o.a_size[0] No No No OUTPUT
sba_tl_h_o.a_size[1] Yes Yes T1,T2,T4 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_param[2:0] No No No OUTPUT
sba_tl_h_o.a_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_opcode[1] No No No OUTPUT
sba_tl_h_o.a_opcode[2] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
sba_tl_h_i.a_ready Yes Yes T1,T2,T43 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_error Yes Yes T1,T2,T25 Yes T1,T2,T25 INPUT
sba_tl_h_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_user.rsp_intg[6:0] Yes Yes T1,T3,T25 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_sink Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_source[7:0] Yes Yes T46,T27,T5 Yes T45,T46,T27 INPUT
sba_tl_h_i.d_size[1:0] Yes Yes T25,T46,T56 Yes T25,T46,T56 INPUT
sba_tl_h_i.d_param[2:0] Yes Yes T46,T27,T5 Yes T45,T46,T57 INPUT
sba_tl_h_i.d_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
sba_tl_h_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T43,T36,T45 Yes T43,T36,T45 INPUT
alert_rx_i[0].ping_n No No No INPUT
alert_rx_i[0].ping_p No No No INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T43,T36,T45 Yes T43,T36,T45 OUTPUT
jtag_i.tdi Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.trst_n Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
jtag_i.tms Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_i.tck Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
jtag_o.tdo_oe Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
jtag_o.tdo Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : rv_dm
Line No.TotalCoveredPercent
Branches 7 7 100.00
IF 320 7 7 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv' or '../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 320 if ((!rst_ni)) -2-: 325 if ((ndmreset_req && (!ndmreset_pending_q))) -3-: 327 if ((ndmreset_ack && ndmreset_pending_q)) -4-: 331 if ((ndmreset_pending_q && lc_rst_asserted)) -5-: 333 if ((ndmreset_ack && lc_rst_pending_q))

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T4,T7,T21
0 0 1 - - Covered T4,T7,T21
0 0 0 - - Covered T1,T2,T3
0 - - 1 - Covered T4,T7,T21
0 - - 0 1 Covered T4,T7,T21
0 - - 0 0 Covered T1,T2,T3


Assert Coverage for Module : rv_dm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 14 87.50
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 14 87.50




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DebugReqOKnown_A 55342681 55304706 0 0
DmactiveOKnown_A 55342681 55304706 0 0
FpvSecCmRegWeOnehotCheck_A 55342681 100 0 0
FpvSecCmRomTlLcGateFsm_A 55342681 0 0 0
FpvSecCmSbaTlLcGateFsm_A 55342681 0 0 0
JtagRspOTdoKnown_A 2247665 2247522 0 0
JtagRspOTdoOeKnown_A 2247665 2247522 0 0
NdmresetOKnown_A 55342681 55304706 0 0
RvDmLcEnDebugVal_A 55342681 55304706 0 0
TlMemAReadyKnown_A 55342681 55304706 0 0
TlMemDValidKnown_A 55342681 55304706 0 0
TlRegsAReadyKnown_A 55342681 55304706 0 0
TlRegsDValidKnown_A 55342681 55304706 0 0
TlSbaAValidKnown_A 55342681 55304706 0 0
TlSbaDReadyKnown_A 55342681 55304706 0 0
paramCheckNrHarts 213 213 0 0


DebugReqOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55304706 0 0
T1 277269 277029 0 0
T2 111725 111537 0 0
T3 288681 288595 0 0
T4 855542 855083 0 0
T25 448762 448573 0 0
T36 10486 10417 0 0
T43 3388 3294 0 0
T44 138230 138170 0 0
T45 1650 1590 0 0
T46 682846 682774 0 0

DmactiveOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55304706 0 0
T1 277269 277029 0 0
T2 111725 111537 0 0
T3 288681 288595 0 0
T4 855542 855083 0 0
T25 448762 448573 0 0
T36 10486 10417 0 0
T43 3388 3294 0 0
T44 138230 138170 0 0
T45 1650 1590 0 0
T46 682846 682774 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 100 0 0
T8 318060 0 0 0
T9 68376 0 0 0
T30 293628 0 0 0
T49 67113 20 0 0
T50 0 20 0 0
T51 0 20 0 0
T70 0 20 0 0
T71 0 20 0 0
T72 55589 0 0 0
T73 1906 0 0 0
T74 26864 0 0 0
T75 3344 0 0 0
T76 3831 0 0 0
T77 3510 0 0 0

FpvSecCmRomTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 0 0 0

FpvSecCmSbaTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 0 0 0

JtagRspOTdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2247665 2247522 0 0
T1 13874 13874 0 0
T2 12762 12762 0 0
T3 8424 8424 0 0
T4 32812 32807 0 0
T25 14917 14917 0 0
T36 132 132 0 0
T43 276 276 0 0
T44 15018 15018 0 0
T45 279 279 0 0
T46 10535 10535 0 0

JtagRspOTdoOeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2247665 2247522 0 0
T1 13874 13874 0 0
T2 12762 12762 0 0
T3 8424 8424 0 0
T4 32812 32807 0 0
T25 14917 14917 0 0
T36 132 132 0 0
T43 276 276 0 0
T44 15018 15018 0 0
T45 279 279 0 0
T46 10535 10535 0 0

NdmresetOKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55304706 0 0
T1 277269 277029 0 0
T2 111725 111537 0 0
T3 288681 288595 0 0
T4 855542 855083 0 0
T25 448762 448573 0 0
T36 10486 10417 0 0
T43 3388 3294 0 0
T44 138230 138170 0 0
T45 1650 1590 0 0
T46 682846 682774 0 0

RvDmLcEnDebugVal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55304706 0 0
T1 277269 277029 0 0
T2 111725 111537 0 0
T3 288681 288595 0 0
T4 855542 855083 0 0
T25 448762 448573 0 0
T36 10486 10417 0 0
T43 3388 3294 0 0
T44 138230 138170 0 0
T45 1650 1590 0 0
T46 682846 682774 0 0

TlMemAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55304706 0 0
T1 277269 277029 0 0
T2 111725 111537 0 0
T3 288681 288595 0 0
T4 855542 855083 0 0
T25 448762 448573 0 0
T36 10486 10417 0 0
T43 3388 3294 0 0
T44 138230 138170 0 0
T45 1650 1590 0 0
T46 682846 682774 0 0

TlMemDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55304706 0 0
T1 277269 277029 0 0
T2 111725 111537 0 0
T3 288681 288595 0 0
T4 855542 855083 0 0
T25 448762 448573 0 0
T36 10486 10417 0 0
T43 3388 3294 0 0
T44 138230 138170 0 0
T45 1650 1590 0 0
T46 682846 682774 0 0

TlRegsAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55304706 0 0
T1 277269 277029 0 0
T2 111725 111537 0 0
T3 288681 288595 0 0
T4 855542 855083 0 0
T25 448762 448573 0 0
T36 10486 10417 0 0
T43 3388 3294 0 0
T44 138230 138170 0 0
T45 1650 1590 0 0
T46 682846 682774 0 0

TlRegsDValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55304706 0 0
T1 277269 277029 0 0
T2 111725 111537 0 0
T3 288681 288595 0 0
T4 855542 855083 0 0
T25 448762 448573 0 0
T36 10486 10417 0 0
T43 3388 3294 0 0
T44 138230 138170 0 0
T45 1650 1590 0 0
T46 682846 682774 0 0

TlSbaAValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55304706 0 0
T1 277269 277029 0 0
T2 111725 111537 0 0
T3 288681 288595 0 0
T4 855542 855083 0 0
T25 448762 448573 0 0
T36 10486 10417 0 0
T43 3388 3294 0 0
T44 138230 138170 0 0
T45 1650 1590 0 0
T46 682846 682774 0 0

TlSbaDReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 55342681 55304706 0 0
T1 277269 277029 0 0
T2 111725 111537 0 0
T3 288681 288595 0 0
T4 855542 855083 0 0
T25 448762 448573 0 0
T36 10486 10417 0 0
T43 3388 3294 0 0
T44 138230 138170 0 0
T45 1650 1590 0 0
T46 682846 682774 0 0

paramCheckNrHarts
NameAttemptsReal SuccessesFailuresIncomplete
Total 213 213 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T25 1 1 0 0
T36 1 1 0 0
T43 1 1 0 0
T44 1 1 0 0
T45 1 1 0 0
T46 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%