Unified Coverage Report :: Module :: rv_dm_enable_checker

Module : rv_dm_enable_checker

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.enable_checker	87.50	100.00					75.00

---

Module Instance : tb.dut.enable_checker

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.50	100.00					75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
87.12	96.97	59.57	91.58		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_dm_enable_checker

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	1	1
36	1	1

---

Assert Coverage for Module : rv_dm_enable_checker

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	3	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	3	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DebugRequestNeedsDebug_A	55342681	5129174	0	0
MemTLResponseWithoutDebugIsError_A	55342681	17	0	0
NdmResetAckNeedsDebug_A	55342681	0	0	0
SbaTLRequestNeedsDebug_A	55342681	11767	0	0

DebugRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55342681	5129174	0	0
T4	855542	315031	0	0
T5	0	3235	0	0
T6	0	23881	0	0
T7	0	14977	0	0
T8	0	124603	0	0
T9	0	28830	0	0
T21	0	102886	0	0
T25	448762	0	0	0
T30	0	84301	0	0
T34	2436	0	0	0
T36	10486	0	0	0
T44	138230	0	0	0
T45	1650	0	0	0
T46	682846	0	0	0
T56	85141	0	0	0
T57	1455	0	0	0
T58	46733	0	0	0
T74	0	21759	0	0
T78	0	6065	0	0

MemTLResponseWithoutDebugIsError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55342681	17	0	0
T14	55964	0	0	0
T47	7030	15	0	0
T48	0	2	0	0
T51	46610	0	0	0
T79	195106	0	0	0
T80	83131	0	0	0
T81	171372	0	0	0
T82	17822	0	0	0
T83	1350	0	0	0
T84	29129	0	0	0
T85	10616	0	0	0

NdmResetAckNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55342681	0	0	0

SbaTLRequestNeedsDebug_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55342681	11767	0	0
T1	277269	13	0	0
T2	111725	10	0	0
T3	288681	15	0	0
T4	855542	0	0	0
T25	448762	97	0	0
T27	0	237	0	0
T36	10486	0	0	0
T43	3388	0	0	0
T44	138230	137	0	0
T45	1650	0	0	0
T46	682846	43	0	0
T56	0	14	0	0
T58	0	78	0	0
T69	0	118	0	0