Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	216549	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	559376	1		T4	7		T5	6		T8	80

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	462583	1		T4	1		T5	6		T8	80
values[0x0]	144809	1		T4	10		T5	13		T7	1
values[0x1]	168533	1		T4	10		T5	10		T6	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	155989	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	619936	1		T4	7		T5	11		T8	80

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3105	1		T20	2		T59	32		T60	27
valid_sources[0x01]	3195	1		T34	1		T59	27		T62	1
valid_sources[0x02]	4435	1		T33	1		T167	3		T59	39
valid_sources[0x03]	3673	1		T63	78		T59	34		T62	1
valid_sources[0x04]	3326	1		T168	1		T59	29		T62	1
valid_sources[0x05]	2726	1		T169	1		T170	2		T59	34
valid_sources[0x06]	2490	1		T59	38		T62	1		T60	18
valid_sources[0x07]	3164	1		T171	1		T59	42		T62	1
valid_sources[0x08]	3136	1		T8	1		T172	1		T59	59
valid_sources[0x09]	2578	1		T4	1		T59	62		T60	26
valid_sources[0x0a]	2689	1		T14	1		T169	1		T59	37
valid_sources[0x0b]	3198	1		T148	1		T9	2		T59	51
valid_sources[0x0c]	3017	1		T59	43		T62	1		T60	27
valid_sources[0x0d]	2867	1		T16	1		T167	1		T59	39
valid_sources[0x0e]	3454	1		T8	2		T20	1		T59	44
valid_sources[0x0f]	3391	1		T132	2		T172	1		T59	28
valid_sources[0x10]	3340	1		T8	2		T173	1		T34	6
valid_sources[0x11]	2983	1		T33	1		T16	1		T59	45
valid_sources[0x12]	3043	1		T48	9		T172	1		T59	39
valid_sources[0x13]	2831	1		T33	1		T59	30		T62	1
valid_sources[0x14]	3308	1		T34	4		T16	2		T59	30
valid_sources[0x15]	3191	1		T33	1		T34	3		T59	35
valid_sources[0x16]	2980	1		T4	3		T34	4		T16	1
valid_sources[0x17]	3864	1		T59	49		T62	1		T60	33
valid_sources[0x18]	3528	1		T8	1		T33	1		T36	3
valid_sources[0x19]	2891	1		T38	3		T59	42		T60	16
valid_sources[0x1a]	3245	1		T8	3		T172	1		T59	44
valid_sources[0x1b]	3719	1		T6	1		T140	1		T63	133
valid_sources[0x1c]	3066	1		T16	1		T59	55		T60	20
valid_sources[0x1d]	3029	1		T4	1		T14	2		T15	2
valid_sources[0x1e]	4361	1		T167	2		T147	1		T59	25
valid_sources[0x1f]	2777	1		T8	1		T170	1		T59	56
valid_sources[0x20]	2751	1		T59	56		T62	1		T60	19
valid_sources[0x21]	2885	1		T59	33		T62	2		T60	29
valid_sources[0x22]	2955	1		T47	2		T11	2		T59	52
valid_sources[0x23]	3162	1		T6	3		T33	1		T34	2
valid_sources[0x24]	2968	1		T9	1		T63	35		T59	41
valid_sources[0x25]	2676	1		T8	2		T174	1		T59	38
valid_sources[0x26]	2975	1		T15	2		T34	1		T59	45
valid_sources[0x27]	5168	1		T59	35		T62	1		T60	23
valid_sources[0x28]	3033	1		T175	4		T176	1		T174	1
valid_sources[0x29]	2792	1		T8	3		T177	2		T59	56
valid_sources[0x2a]	2748	1		T8	3		T9	1		T59	37
valid_sources[0x2b]	3195	1		T59	49		T62	2		T60	23
valid_sources[0x2c]	3033	1		T140	2		T59	51		T62	2
valid_sources[0x2d]	2732	1		T33	1		T20	2		T39	2
valid_sources[0x2e]	3141	1		T6	7		T11	1		T22	13
valid_sources[0x2f]	3386	1		T140	1		T59	56		T60	9
valid_sources[0x30]	2387	1		T4	1		T172	1		T59	28
valid_sources[0x31]	2750	1		T59	32		T62	2		T60	20
valid_sources[0x32]	3220	1		T59	27		T62	1		T60	22
valid_sources[0x33]	2668	1		T11	1		T59	33		T60	23
valid_sources[0x34]	2774	1		T170	1		T63	30		T59	46
valid_sources[0x35]	2943	1		T59	40		T62	1		T60	7
valid_sources[0x36]	3122	1		T140	1		T59	42		T62	3
valid_sources[0x37]	2984	1		T8	2		T33	3		T59	30
valid_sources[0x38]	3297	1		T59	54		T60	24		T91	7
valid_sources[0x39]	2475	1		T8	1		T59	38		T62	4
valid_sources[0x3a]	3096	1		T33	1		T34	2		T59	49
valid_sources[0x3b]	2770	1		T148	2		T59	44		T60	32
valid_sources[0x3c]	2978	1		T9	1		T59	32		T60	11
valid_sources[0x3d]	2683	1		T11	1		T20	2		T59	49
valid_sources[0x3e]	3066	1		T20	1		T59	34		T62	2
valid_sources[0x3f]	3061	1		T148	4		T16	1		T59	26
valid_sources[0x40]	3101	1		T8	2		T59	37		T60	22
valid_sources[0x41]	3658	1		T8	2		T11	3		T16	1
valid_sources[0x42]	2889	1		T47	2		T33	1		T59	37
valid_sources[0x43]	2739	1		T8	2		T171	1		T140	1
valid_sources[0x44]	2914	1		T34	1		T59	43		T62	3
valid_sources[0x45]	2850	1		T16	1		T59	30		T62	1
valid_sources[0x46]	2984	1		T8	7		T34	2		T59	41
valid_sources[0x47]	2915	1		T15	4		T16	2		T59	40
valid_sources[0x48]	3041	1		T34	1		T140	1		T170	2
valid_sources[0x49]	3170	1		T59	35		T60	17		T91	9
valid_sources[0x4a]	2979	1		T171	1		T140	1		T63	4
valid_sources[0x4b]	2942	1		T59	40		T62	1		T60	17
valid_sources[0x4c]	2963	1		T147	1		T178	1		T59	38
valid_sources[0x4d]	2835	1		T16	1		T59	37		T60	23
valid_sources[0x4e]	2549	1		T11	2		T52	12		T20	1
valid_sources[0x4f]	2840	1		T4	2		T148	3		T59	40
valid_sources[0x50]	3119	1		T176	1		T59	40		T60	10
valid_sources[0x51]	3164	1		T34	7		T59	29		T60	22
valid_sources[0x52]	2809	1		T9	1		T172	2		T59	47
valid_sources[0x53]	3125	1		T172	1		T59	38		T60	13
valid_sources[0x54]	2844	1		T146	14		T16	1		T140	1
valid_sources[0x55]	3170	1		T16	1		T9	1		T59	32
valid_sources[0x56]	3303	1		T20	2		T9	2		T59	51
valid_sources[0x57]	3268	1		T59	49		T60	27		T91	2
valid_sources[0x58]	2734	1		T59	35		T60	17		T91	7
valid_sources[0x59]	2981	1		T172	1		T59	56		T62	3
valid_sources[0x5a]	2902	1		T11	5		T18	3		T174	1
valid_sources[0x5b]	2543	1		T33	2		T150	42		T20	1
valid_sources[0x5c]	2667	1		T167	1		T171	3		T20	2
valid_sources[0x5d]	2536	1		T59	44		T62	1		T60	16
valid_sources[0x5e]	3410	1		T171	4		T59	36		T60	9
valid_sources[0x5f]	3213	1		T170	2		T59	41		T62	3
valid_sources[0x60]	2945	1		T172	1		T59	50		T60	20
valid_sources[0x61]	2696	1		T33	1		T10	2		T59	47
valid_sources[0x62]	2509	1		T132	12		T59	31		T62	3
valid_sources[0x63]	2597	1		T7	9		T52	2		T16	1
valid_sources[0x64]	3296	1		T14	1		T171	1		T59	27
valid_sources[0x65]	2991	1		T16	2		T171	1		T59	36
valid_sources[0x66]	3528	1		T36	4		T59	44		T62	1
valid_sources[0x67]	3099	1		T148	2		T140	1		T59	40
valid_sources[0x68]	2790	1		T59	52		T62	5		T60	12
valid_sources[0x69]	2868	1		T34	2		T59	44		T62	2
valid_sources[0x6a]	3583	1		T11	1		T16	1		T59	54
valid_sources[0x6b]	2692	1		T59	30		T60	19		T91	3
valid_sources[0x6c]	3149	1		T174	2		T59	42		T62	1
valid_sources[0x6d]	3081	1		T8	2		T15	1		T170	1
valid_sources[0x6e]	2804	1		T33	1		T59	57		T62	1
valid_sources[0x6f]	3470	1		T16	2		T140	1		T59	48
valid_sources[0x70]	2703	1		T8	1		T59	50		T62	1
valid_sources[0x71]	3251	1		T36	1		T59	36		T62	1
valid_sources[0x72]	2666	1		T52	31		T140	1		T9	2
valid_sources[0x73]	2705	1		T4	1		T34	3		T23	1
valid_sources[0x74]	2611	1		T59	43		T60	20		T91	4
valid_sources[0x75]	3224	1		T148	3		T59	55		T60	23
valid_sources[0x76]	2734	1		T33	1		T34	2		T16	1
valid_sources[0x77]	2811	1		T8	3		T59	39		T62	1
valid_sources[0x78]	3081	1		T8	1		T34	1		T59	31
valid_sources[0x79]	3445	1		T9	2		T59	43		T62	1
valid_sources[0x7a]	2857	1		T9	1		T59	35		T60	29
valid_sources[0x7b]	2933	1		T140	1		T59	45		T62	1
valid_sources[0x7c]	2844	1		T56	1		T140	1		T59	40
valid_sources[0x7d]	2972	1		T33	1		T15	1		T172	3
valid_sources[0x7e]	2924	1		T11	1		T12	11		T147	1
valid_sources[0x7f]	2814	1		T23	2		T9	1		T59	48
valid_sources[0x80]	3242	1		T33	1		T37	1		T59	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

278177

1

T4

1

T5

3

T8

80

values[0x0]

all_enables

biggest_size

140872

1

T4

4

T5

3

T6

4

values[0x1]

all_enables

biggest_size

140327

1

T4

2

T6

4

T30

2

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5502	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	53906	1		T1	1		T2	1		T3	4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	17421	1		T63	3		T59	72		T62	95
values[0x0]	20515	1		T3	2		T4	3		T35	6
values[0x1]	21472	1		T1	1		T2	1		T3	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3800	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	55608	1		T1	1		T2	1		T3	4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	187	1		T16	2		T176	1		T68	1
valid_sources[0x01]	298	1		T132	1		T174	1		T62	2
valid_sources[0x02]	257	1		T148	3		T179	1		T180	1
valid_sources[0x03]	239	1		T181	1		T182	1		T143	1
valid_sources[0x04]	449	1		T84	1		T62	3		T93	3
valid_sources[0x05]	165	1		T5	5		T9	1		T61	1
valid_sources[0x06]	202	1		T24	5		T62	1		T93	2
valid_sources[0x07]	201	1		T146	1		T93	2		T80	1
valid_sources[0x08]	174	1		T62	1		T61	7		T93	7
valid_sources[0x09]	174	1		T42	3		T183	1		T93	6
valid_sources[0x0a]	240	1		T35	1		T42	5		T184	1
valid_sources[0x0b]	225	1		T52	2		T16	1		T183	1
valid_sources[0x0c]	173	1		T14	1		T62	1		T61	4
valid_sources[0x0d]	383	1		T185	1		T61	1		T93	2
valid_sources[0x0e]	229	1		T186	1		T93	4		T81	2
valid_sources[0x0f]	213	1		T57	2		T137	1		T62	2
valid_sources[0x10]	182	1		T33	1		T56	1		T187	1
valid_sources[0x11]	126	1		T62	2		T93	1		T80	1
valid_sources[0x12]	289	1		T42	2		T52	1		T188	1
valid_sources[0x13]	256	1		T132	1		T72	8		T62	2
valid_sources[0x14]	216	1		T4	7		T127	2		T189	1
valid_sources[0x15]	281	1		T190	2		T191	1		T62	2
valid_sources[0x16]	177	1		T145	3		T192	1		T62	2
valid_sources[0x17]	236	1		T15	1		T93	2		T81	3
valid_sources[0x18]	188	1		T193	1		T12	1		T182	1
valid_sources[0x19]	237	1		T57	1		T15	1		T194	1
valid_sources[0x1a]	208	1		T195	1		T196	1		T59	3
valid_sources[0x1b]	215	1		T48	1		T197	1		T59	3
valid_sources[0x1c]	308	1		T15	1		T198	1		T62	3
valid_sources[0x1d]	299	1		T195	2		T199	1		T200	6
valid_sources[0x1e]	219	1		T192	1		T62	3		T60	1
valid_sources[0x1f]	257	1		T30	9		T201	1		T189	1
valid_sources[0x20]	167	1		T195	2		T9	1		T202	3
valid_sources[0x21]	189	1		T73	1		T203	1		T62	2
valid_sources[0x22]	223	1		T143	2		T204	1		T59	7
valid_sources[0x23]	216	1		T42	1		T205	2		T62	2
valid_sources[0x24]	188	1		T59	6		T62	1		T93	6
valid_sources[0x25]	198	1		T142	1		T59	3		T62	5
valid_sources[0x26]	347	1		T206	1		T207	1		T208	7
valid_sources[0x27]	333	1		T36	1		T183	1		T180	2
valid_sources[0x28]	207	1		T139	2		T147	1		T209	1
valid_sources[0x29]	196	1		T62	1		T60	1		T93	4
valid_sources[0x2a]	238	1		T35	1		T193	1		T174	2
valid_sources[0x2b]	175	1		T48	1		T61	1		T93	4
valid_sources[0x2c]	693	1		T43	1		T195	2		T15	1
valid_sources[0x2d]	285	1		T12	2		T15	1		T137	1
valid_sources[0x2e]	193	1		T129	1		T206	2		T140	2
valid_sources[0x2f]	371	1		T57	1		T132	1		T186	1
valid_sources[0x30]	210	1		T62	1		T60	1		T93	4
valid_sources[0x31]	262	1		T210	1		T62	2		T93	3
valid_sources[0x32]	178	1		T48	1		T202	1		T60	2
valid_sources[0x33]	165	1		T55	1		T16	1		T62	1
valid_sources[0x34]	166	1		T61	3		T93	1		T88	1
valid_sources[0x35]	203	1		T207	1		T151	1		T61	4
valid_sources[0x36]	239	1		T193	2		T211	2		T62	5
valid_sources[0x37]	187	1		T201	1		T205	1		T62	1
valid_sources[0x38]	146	1		T206	1		T212	4		T62	1
valid_sources[0x39]	519	1		T38	1		T186	1		T213	1
valid_sources[0x3a]	315	1		T41	1		T143	1		T62	1
valid_sources[0x3b]	279	1		T33	1		T207	1		T185	2
valid_sources[0x3c]	185	1		T181	1		T62	3		T93	3
valid_sources[0x3d]	325	1		T214	2		T62	3		T93	2
valid_sources[0x3e]	204	1		T142	1		T215	10		T185	1
valid_sources[0x3f]	121	1		T193	1		T170	1		T93	3
valid_sources[0x40]	253	1		T42	1		T216	1		T205	1
valid_sources[0x41]	181	1		T48	1		T207	2		T217	5
valid_sources[0x42]	218	1		T218	1		T62	1		T88	2
valid_sources[0x43]	278	1		T183	1		T73	1		T219	1
valid_sources[0x44]	176	1		T142	1		T220	3		T59	3
valid_sources[0x45]	186	1		T136	1		T221	1		T62	1
valid_sources[0x46]	243	1		T62	1		T93	2		T80	1
valid_sources[0x47]	190	1		T52	1		T220	1		T60	1
valid_sources[0x48]	174	1		T62	3		T60	1		T93	5
valid_sources[0x49]	596	1		T207	1		T93	5		T74	5
valid_sources[0x4a]	271	1		T43	2		T62	2		T93	2
valid_sources[0x4b]	217	1		T5	3		T186	1		T222	1
valid_sources[0x4c]	198	1		T60	1		T93	3		T74	11
valid_sources[0x4d]	147	1		T62	1		T61	1		T93	5
valid_sources[0x4e]	281	1		T206	1		T211	12		T62	1
valid_sources[0x4f]	184	1		T93	4		T88	1		T89	1
valid_sources[0x50]	302	1		T223	1		T214	1		T192	1
valid_sources[0x51]	157	1		T148	4		T138	1		T62	5
valid_sources[0x52]	199	1		T176	1		T224	1		T219	1
valid_sources[0x53]	162	1		T225	6		T144	1		T207	1
valid_sources[0x54]	190	1		T226	1		T73	1		T180	1
valid_sources[0x55]	235	1		T183	1		T19	1		T170	2
valid_sources[0x56]	225	1		T227	1		T228	2		T183	1
valid_sources[0x57]	195	1		T193	1		T60	1		T93	3
valid_sources[0x58]	162	1		T57	2		T20	3		T151	1
valid_sources[0x59]	207	1		T176	1		T39	1		T62	2
valid_sources[0x5a]	170	1		T40	1		T229	1		T230	1
valid_sources[0x5b]	194	1		T60	2		T61	1		T93	7
valid_sources[0x5c]	203	1		T82	1		T231	1		T192	1
valid_sources[0x5d]	198	1		T180	1		T62	2		T93	1
valid_sources[0x5e]	234	1		T132	1		T222	1		T178	5
valid_sources[0x5f]	268	1		T33	2		T58	1		T232	5
valid_sources[0x60]	289	1		T2	1		T14	3		T62	1
valid_sources[0x61]	228	1		T62	2		T92	1		T93	5
valid_sources[0x62]	162	1		T18	1		T197	1		T185	1
valid_sources[0x63]	300	1		T15	1		T233	4		T62	1
valid_sources[0x64]	185	1		T93	3		T81	2		T74	4
valid_sources[0x65]	163	1		T25	1		T43	1		T234	1
valid_sources[0x66]	172	1		T178	2		T62	2		T60	1
valid_sources[0x67]	322	1		T235	1		T206	1		T181	1
valid_sources[0x68]	208	1		T33	1		T173	1		T20	3
valid_sources[0x69]	205	1		T236	1		T73	1		T61	2
valid_sources[0x6a]	209	1		T176	1		T9	1		T237	1
valid_sources[0x6b]	190	1		T22	1		T176	1		T203	1
valid_sources[0x6c]	220	1		T53	7		T220	2		T62	4
valid_sources[0x6d]	269	1		T3	1		T207	1		T62	2
valid_sources[0x6e]	211	1		T238	1		T62	3		T60	1
valid_sources[0x6f]	143	1		T130	1		T239	1		T170	1
valid_sources[0x70]	168	1		T62	1		T61	2		T93	6
valid_sources[0x71]	172	1		T62	4		T61	3		T79	6
valid_sources[0x72]	215	1		T32	1		T62	3		T60	1
valid_sources[0x73]	249	1		T169	1		T34	1		T59	16
valid_sources[0x74]	200	1		T3	1		T47	3		T206	1
valid_sources[0x75]	261	1		T73	1		T219	1		T62	2
valid_sources[0x76]	215	1		T87	1		T240	1		T204	1
valid_sources[0x77]	231	1		T62	1		T93	4		T95	7
valid_sources[0x78]	345	1		T73	1		T62	1		T93	2
valid_sources[0x79]	244	1		T234	1		T62	1		T93	1
valid_sources[0x7a]	296	1		T12	3		T203	1		T220	3
valid_sources[0x7b]	215	1		T22	1		T234	1		T192	1
valid_sources[0x7c]	178	1		T93	4		T88	3		T75	2
valid_sources[0x7d]	179	1		T9	2		T62	1		T61	2
valid_sources[0x7e]	165	1		T241	1		T16	1		T73	1
valid_sources[0x7f]	217	1		T83	1		T93	3		T88	1
valid_sources[0x80]	232	1		T26	1		T182	1		T70	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

14704

1

T63

3

T59

30

T62

93

values[0x0]

all_enables

biggest_size

19704

1

T3

2

T4

3

T35

1

values[0x1]

all_enables

biggest_size

19498

1

T1

1

T2

1

T3

2