Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	409928	1		T4	14		T5	23		T7	5
full_word	566724	1		T4	7		T5	6		T8	80

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	976382	1		T4	21		T5	29		T8	80
auto[TlIntgErrCmd]	94	1		T59	5		T60	3		T125	4
auto[TlIntgErrData]	82	1		T59	7		T60	4		T125	4
auto[TlIntgErrBoth]	94	1		T59	8		T60	3		T125	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	471142	1		T4	1		T5	6		T8	80
auto[1]	505510	1		T4	20		T5	23		T7	1

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	191981	1		T5	3		T7	4		T33	6
auto[TlIntgErrNone]	partial	auto[1]	217692	1		T4	14		T5	20		T7	1
auto[TlIntgErrNone]	full_word	auto[0]	279032	1		T4	1		T5	3		T8	80
auto[TlIntgErrNone]	full_word	auto[1]	287677	1		T4	6		T5	3		T6	8
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T59	2		T125	3		T155	1
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T59	3		T60	3		T125	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T155	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T164	1		T162	1		T159	1
auto[TlIntgErrData]	partial	auto[0]	48	1		T59	7		T60	2		T125	2
auto[TlIntgErrData]	partial	auto[1]	31	1		T60	2		T125	2		T155	2
auto[TlIntgErrData]	full_word	auto[0]	1	1		T160	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	2	1		T161	1		T164	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T59	2		T60	2		T125	1
auto[TlIntgErrBoth]	partial	auto[1]	51	1		T59	5		T60	1		T125	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T160	1		T159	1		T166	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T59	1		T155	1		-	-