Unified Coverage Report :: Module :: rv_dm_regs_csr_assert_fpv

Module : rv_dm_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rv_dm_csr_assert_0/rv_dm_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rv_dm_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rv_dm_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.35	100.00	76.60	92.63		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rv_dm_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	117471273	61543	0	0
late_debug_enable_rd_A	117471273	4597	0	0
late_debug_enable_regwen_rd_A	117471273	2799	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117471273	61543	0	0
T59	63700	3	0	0
T60	262832	1	0	0
T61	13587	45	0	0
T62	19637	580	0	0
T74	276620	999	0	0
T79	11923	24	0	0
T80	12076	454	0	0
T81	12358	370	0	0
T88	10010	164	0	0
T89	77581	11	0	0

late_debug_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117471273	4597	0	0
T63	8178	9	0	0
T74	276620	456	0	0
T79	11923	2	0	0
T81	12358	24	0	0
T89	77581	12	0	0
T91	11009	8	0	0
T93	737451	472	0	0
T95	61767	9	0	0
T125	48935	58	0	0
T126	28261	25	0	0

late_debug_enable_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	117471273	2799	0	0
T63	8178	9	0	0
T74	276620	313	0	0
T79	11923	20	0	0
T81	12358	26	0	0
T89	77581	9	0	0
T91	11009	4	0	0
T93	737451	453	0	0
T95	61767	36	0	0
T125	48935	48	0	0
T126	28261	8	0	0