Line Coverage for Module :
rv_dm_enable_checker
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 29 | 1 | 1 | 100.00 |
CONT_ASSIGN | 36 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' or '../src/lowrisc_dv_rv_dm_sva_0.1/rv_dm_enable_checker.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
29 |
1 |
1 |
36 |
1 |
1 |
Assert Coverage for Module :
rv_dm_enable_checker
Assertion Details
DebugRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
58203515 |
58166961 |
0 |
0 |
T1 |
871461 |
871410 |
0 |
0 |
T2 |
31590 |
31514 |
0 |
0 |
T3 |
41053 |
40789 |
0 |
0 |
T4 |
59085 |
58775 |
0 |
0 |
T5 |
113975 |
113641 |
0 |
0 |
T7 |
17934 |
17845 |
0 |
0 |
T8 |
2085 |
2011 |
0 |
0 |
T35 |
2822 |
2755 |
0 |
0 |
T40 |
20344 |
20274 |
0 |
0 |
T41 |
285455 |
285396 |
0 |
0 |
MemTLResponseWithoutDebugIsError_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
58203515 |
58166961 |
0 |
0 |
T1 |
871461 |
871410 |
0 |
0 |
T2 |
31590 |
31514 |
0 |
0 |
T3 |
41053 |
40789 |
0 |
0 |
T4 |
59085 |
58775 |
0 |
0 |
T5 |
113975 |
113641 |
0 |
0 |
T7 |
17934 |
17845 |
0 |
0 |
T8 |
2085 |
2011 |
0 |
0 |
T35 |
2822 |
2755 |
0 |
0 |
T40 |
20344 |
20274 |
0 |
0 |
T41 |
285455 |
285396 |
0 |
0 |
NdmResetAckNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
58203515 |
58166961 |
0 |
0 |
T1 |
871461 |
871410 |
0 |
0 |
T2 |
31590 |
31514 |
0 |
0 |
T3 |
41053 |
40789 |
0 |
0 |
T4 |
59085 |
58775 |
0 |
0 |
T5 |
113975 |
113641 |
0 |
0 |
T7 |
17934 |
17845 |
0 |
0 |
T8 |
2085 |
2011 |
0 |
0 |
T35 |
2822 |
2755 |
0 |
0 |
T40 |
20344 |
20274 |
0 |
0 |
T41 |
285455 |
285396 |
0 |
0 |
SbaTLRequestNeedsDebug_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
58203515 |
58166961 |
0 |
0 |
T1 |
871461 |
871410 |
0 |
0 |
T2 |
31590 |
31514 |
0 |
0 |
T3 |
41053 |
40789 |
0 |
0 |
T4 |
59085 |
58775 |
0 |
0 |
T5 |
113975 |
113641 |
0 |
0 |
T7 |
17934 |
17845 |
0 |
0 |
T8 |
2085 |
2011 |
0 |
0 |
T35 |
2822 |
2755 |
0 |
0 |
T40 |
20344 |
20274 |
0 |
0 |
T41 |
285455 |
285396 |
0 |
0 |