Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9818056 |
9816732 |
0 |
0 |
selKnown1 |
65161527 |
65160203 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9818056 |
9816732 |
0 |
0 |
T1 |
32886 |
32884 |
0 |
0 |
T2 |
15337 |
15335 |
0 |
0 |
T3 |
13485 |
13481 |
0 |
0 |
T4 |
29434 |
29430 |
0 |
0 |
T5 |
38618 |
38614 |
0 |
0 |
T6 |
0 |
10 |
0 |
0 |
T7 |
2573 |
2569 |
0 |
0 |
T8 |
776 |
772 |
0 |
0 |
T24 |
10 |
8 |
0 |
0 |
T25 |
2 |
0 |
0 |
0 |
T30 |
0 |
10 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T35 |
528 |
524 |
0 |
0 |
T40 |
34743 |
34739 |
0 |
0 |
T41 |
30730 |
30726 |
0 |
0 |
T47 |
0 |
22 |
0 |
0 |
T48 |
0 |
13 |
0 |
0 |
T53 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
65161527 |
65160203 |
0 |
0 |
T1 |
887904 |
887902 |
0 |
0 |
T2 |
39258 |
39256 |
0 |
0 |
T3 |
47799 |
47795 |
0 |
0 |
T4 |
73806 |
73802 |
0 |
0 |
T5 |
133288 |
133284 |
0 |
0 |
T6 |
0 |
8 |
0 |
0 |
T7 |
19221 |
19217 |
0 |
0 |
T8 |
2474 |
2470 |
0 |
0 |
T24 |
10 |
8 |
0 |
0 |
T25 |
2 |
0 |
0 |
0 |
T30 |
0 |
6 |
0 |
0 |
T33 |
0 |
6 |
0 |
0 |
T35 |
3087 |
3083 |
0 |
0 |
T40 |
37716 |
37712 |
0 |
0 |
T41 |
300821 |
300817 |
0 |
0 |
T47 |
0 |
12 |
0 |
0 |
T48 |
0 |
8 |
0 |
0 |
T53 |
0 |
6 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
2859611 |
2859390 |
0 |
0 |
selKnown1 |
58203515 |
58203294 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2859611 |
2859390 |
0 |
0 |
T1 |
16443 |
16442 |
0 |
0 |
T2 |
7668 |
7667 |
0 |
0 |
T3 |
6738 |
6737 |
0 |
0 |
T4 |
14711 |
14710 |
0 |
0 |
T5 |
19303 |
19302 |
0 |
0 |
T7 |
1285 |
1284 |
0 |
0 |
T8 |
387 |
386 |
0 |
0 |
T35 |
263 |
262 |
0 |
0 |
T40 |
17370 |
17369 |
0 |
0 |
T41 |
15364 |
15363 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
58203515 |
58203294 |
0 |
0 |
T1 |
871461 |
871460 |
0 |
0 |
T2 |
31590 |
31589 |
0 |
0 |
T3 |
41053 |
41052 |
0 |
0 |
T4 |
59085 |
59084 |
0 |
0 |
T5 |
113975 |
113974 |
0 |
0 |
T7 |
17934 |
17933 |
0 |
0 |
T8 |
2085 |
2084 |
0 |
0 |
T35 |
2822 |
2821 |
0 |
0 |
T40 |
20344 |
20343 |
0 |
0 |
T41 |
285455 |
285454 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic
Assertion Details
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
583 |
362 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
0 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T30 |
0 |
5 |
0 |
0 |
T33 |
0 |
3 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T47 |
0 |
7 |
0 |
0 |
T48 |
0 |
4 |
0 |
0 |
T53 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
559 |
338 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
5 |
4 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T33 |
0 |
3 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T47 |
0 |
6 |
0 |
0 |
T48 |
0 |
4 |
0 |
0 |
T53 |
0 |
3 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
6956038 |
6955597 |
0 |
0 |
selKnown1 |
6955820 |
6955379 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6956038 |
6955597 |
0 |
0 |
T1 |
16443 |
16442 |
0 |
0 |
T2 |
7669 |
7668 |
0 |
0 |
T3 |
6739 |
6738 |
0 |
0 |
T4 |
14711 |
14710 |
0 |
0 |
T5 |
19303 |
19302 |
0 |
0 |
T7 |
1286 |
1285 |
0 |
0 |
T8 |
387 |
386 |
0 |
0 |
T35 |
263 |
262 |
0 |
0 |
T40 |
17371 |
17370 |
0 |
0 |
T41 |
15364 |
15363 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
6955820 |
6955379 |
0 |
0 |
T1 |
16443 |
16442 |
0 |
0 |
T2 |
7668 |
7667 |
0 |
0 |
T3 |
6738 |
6737 |
0 |
0 |
T4 |
14711 |
14710 |
0 |
0 |
T5 |
19303 |
19302 |
0 |
0 |
T7 |
1285 |
1284 |
0 |
0 |
T8 |
387 |
386 |
0 |
0 |
T35 |
263 |
262 |
0 |
0 |
T40 |
17370 |
17369 |
0 |
0 |
T41 |
15364 |
15363 |
0 |
0 |
Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 5 | 55.56 |
Logical | 9 | 5 | 55.56 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1824 |
1383 |
0 |
0 |
selKnown1 |
1633 |
1192 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1824 |
1383 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
7 |
6 |
0 |
0 |
T5 |
6 |
5 |
0 |
0 |
T6 |
0 |
5 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T30 |
0 |
5 |
0 |
0 |
T33 |
0 |
3 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T47 |
0 |
15 |
0 |
0 |
T48 |
0 |
9 |
0 |
0 |
T53 |
0 |
4 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1633 |
1192 |
0 |
0 |
T3 |
4 |
3 |
0 |
0 |
T4 |
5 |
4 |
0 |
0 |
T5 |
5 |
4 |
0 |
0 |
T6 |
0 |
4 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
1 |
0 |
0 |
0 |
T24 |
5 |
4 |
0 |
0 |
T25 |
1 |
0 |
0 |
0 |
T30 |
0 |
3 |
0 |
0 |
T33 |
0 |
3 |
0 |
0 |
T35 |
1 |
0 |
0 |
0 |
T40 |
1 |
0 |
0 |
0 |
T41 |
1 |
0 |
0 |
0 |
T47 |
0 |
6 |
0 |
0 |
T48 |
0 |
4 |
0 |
0 |
T53 |
0 |
3 |
0 |
0 |