Line Coverage for Module :
tlul_err_resp
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
ALWAYS | 34 | 14 | 14 | 100.00 |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
CONT_ASSIGN | 59 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
35 |
1 |
1 |
36 |
1 |
1 |
37 |
1 |
1 |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
|
|
|
MISSING_ELSE |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
55 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
65 |
1 |
1 |
Cond Coverage for Module :
tlul_err_resp
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 40
EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
-------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T56 |
1 | 1 | Covered | T56,T82,T58 |
LINE 42
EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
-------1------ ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T56,T82,T58 |
LINE 59
EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
---------1---------
-1- | Status | Tests |
0 | Covered | T56,T82,T58 |
1 | Covered | T1,T2,T3 |
LINE 59
SUB-EXPRESSION (err_opcode == Get)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
tlul_err_resp
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
59 |
2 |
2 |
100.00 |
IF |
34 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 59 ((err_opcode == Get)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T56,T82,T58 |
LineNo. Expression
-1-: 34 if ((!rst_ni))
-2-: 40 if ((err_rsp_pending && tl_h_i.d_ready))
-3-: 42 if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T56,T82,T58 |
0 |
0 |
1 |
Covered |
T56,T82,T58 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
ALWAYS | 34 | 14 | 14 | 100.00 |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
CONT_ASSIGN | 59 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
35 |
1 |
1 |
36 |
1 |
1 |
37 |
1 |
1 |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
|
|
|
MISSING_ELSE |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
55 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
65 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp
| Total | Covered | Percent |
Conditions | 10 | 8 | 80.00 |
Logical | 10 | 8 | 80.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 40
EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
-------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T82,T83 |
LINE 42
EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
-------1------ ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T82,T83 |
LINE 59
EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
---------1---------
-1- | Status | Tests |
0 | Covered | T82,T83 |
1 | Covered | T1,T2,T3 |
LINE 59
SUB-EXPRESSION (err_opcode == Get)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_sba.u_tlul_err_resp
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
59 |
2 |
2 |
100.00 |
IF |
34 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 59 ((err_opcode == Get)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T82,T83 |
LineNo. Expression
-1-: 34 if ((!rst_ni))
-2-: 40 if ((err_rsp_pending && tl_h_i.d_ready))
-3-: 42 if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T82,T83 |
0 |
0 |
1 |
Covered |
T82,T83 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
ALWAYS | 34 | 14 | 14 | 100.00 |
CONT_ASSIGN | 51 | 1 | 1 | 100.00 |
CONT_ASSIGN | 52 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
CONT_ASSIGN | 55 | 1 | 1 | 100.00 |
CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
CONT_ASSIGN | 59 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
34 |
1 |
1 |
35 |
1 |
1 |
36 |
1 |
1 |
37 |
1 |
1 |
38 |
1 |
1 |
39 |
1 |
1 |
40 |
1 |
1 |
41 |
1 |
1 |
42 |
1 |
1 |
43 |
1 |
1 |
44 |
1 |
1 |
45 |
1 |
1 |
46 |
1 |
1 |
47 |
1 |
1 |
|
|
|
MISSING_ELSE |
51 |
1 |
1 |
52 |
1 |
1 |
53 |
1 |
1 |
55 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
65 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp
| Total | Covered | Percent |
Conditions | 10 | 9 | 90.00 |
Logical | 10 | 9 | 90.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 40
EXPRESSION (err_rsp_pending && tl_h_i.d_ready)
-------1------- -------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T56 |
1 | 1 | Covered | T56,T58 |
LINE 42
EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
-------1------ ---------2--------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T56,T58 |
LINE 59
EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
---------1---------
-1- | Status | Tests |
0 | Covered | T56,T58 |
1 | Covered | T1,T2,T3 |
LINE 59
SUB-EXPRESSION (err_opcode == Get)
---------1---------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul_lc_gate_rom.u_tlul_err_resp
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
6 |
100.00 |
TERNARY |
59 |
2 |
2 |
100.00 |
IF |
34 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 59 ((err_opcode == Get)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T56,T58 |
LineNo. Expression
-1-: 34 if ((!rst_ni))
-2-: 40 if ((err_rsp_pending && tl_h_i.d_ready))
-3-: 42 if ((tl_h_i.a_valid && tl_h_o_int.a_ready))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T56,T58 |
0 |
0 |
1 |
Covered |
T56,T58 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |